lorenzschmid
commented
3 months ago @tgingold-cern to add to the following point:
If the default
pipelinesetting (wr-in,rd-out) was used, while being faster the interfaces should still behave correctly.
Any write request relaying on the write acknowledge signal is now one cycle faster. About APB, we previously used pipeline: rd-out to have the standard conform two cycles write requests. With the changes presented here, the write request takes only one cycle, and we switched to pipeline: wr-in,rd-out to restore the old behavior taking two cycles.
tgingold-cern
The write acknowledge signal is now combinatorically linked to the write request signal. The write strobe signal (that should become active only after the register is updated) is delayed by one cycle as previously.
This allows for consecutive single cycle writes as mentioned in #48.
Since this pull request changes the write acknowledge signal to be asserted one cycle earlier, existing memory maps might execute their write requests one cycle faster now. If the default
pipelinesetting (wr-in,rd-out) was used, while being faster the interfaces should still behave correctly. Required testbench changes are visible in 071dbb76732884255e10a04013a5fd088a3a27cf and affect only register write verification's happening now slightly too early (just around the rising edge where previously, the write request took one cycle longer and so the verification was also happening only one cycle later).Closes #48.