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Generating memory using a repeat block with iogroup x-hdl flag crashes cheby #9

Open augustofg opened 1 year ago

augustofg commented 1 year ago

I don't know if this is the correct repository to report bugs and open PRs, buts since I don't have an account at gitlab.cern.ch I'm trying here.

I would like to group the memory interfaces of 8 instances into an array of records, but cheby crashes when trying to generate the vhdl code. Here is a minimal reproducible example:

memory-map:
  bus: wb-32-be
  name: wb_ram_io_group_regs
  description: RAMs in an IO Group
  x-hdl:
    busgroup: True
  children:
    - repeat:
        name: rams
        count: 8
        size: 4096
        x-hdl:
          iogroup: ram_io_grp
        children:
          - memory:
              name: ram_bank
              memsize: 2k
              description: Data
              children:
                - reg:
                    name: data
                    width: 32
                    access: rw

$ cheby -i ram_io_group.cheby --hdl vhdl --gen-hdl wb_ram_io_group_regs.vhd
Traceback (most recent call last):
  File "/home/augusto/.local/bin/cheby", line 33, in <module>
    sys.exit(load_entry_point('cheby==1.6.dev0', 'console_scripts', 'cheby')())
             ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/augusto/.local/lib/python3.11/site-packages/cheby-1.6.dev0-py3.11.egg/cheby/main.py", line 396, in main
    handle_file(args, f)
  File "/home/augusto/.local/lib/python3.11/site-packages/cheby-1.6.dev0-py3.11.egg/cheby/main.py", line 350, in handle_file
    h = gen_hdl.generate_hdl(top)
        ^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/augusto/.local/lib/python3.11/site-packages/cheby-1.6.dev0-py3.11.egg/cheby/gen_hdl.py", line 318, in generate_hdl
    root.h_gen.gen_ports()
  File "/home/augusto/.local/lib/python3.11/site-packages/cheby-1.6.dev0-py3.11.egg/cheby/hdl/genblock.py", line 59, in gen_ports
    n.h_gen.gen_ports()
  File "/home/augusto/.local/lib/python3.11/site-packages/cheby-1.6.dev0-py3.11.egg/cheby/hdl/genblock.py", line 101, in gen_ports
    n.h_gen.gen_ports()
  File "/home/augusto/.local/lib/python3.11/site-packages/cheby-1.6.dev0-py3.11.egg/cheby/hdl/genblock.py", line 59, in gen_ports
    n.h_gen.gen_ports()
  File "/home/augusto/.local/lib/python3.11/site-packages/cheby-1.6.dev0-py3.11.egg/cheby/hdl/genmemory.py", line 25, in gen_ports
    mem.h_ext_addr = self.add_module_port(mem.c_name + '_adr_i', mem.h_addr_width, 'IN')
                     ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/augusto/.local/lib/python3.11/site-packages/cheby-1.6.dev0-py3.11.egg/cheby/hdl/elgen.py", line 16, in add_module_port
    p = self.root.h_itf.add_port(name, size, dir=dir)
        ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  File "/home/augusto/.local/lib/python3.11/site-packages/cheby-1.6.dev0-py3.11.egg/cheby/hdltree.py", line 131, in add_port
    return self.names[dirn][name]
           ~~~~~~~~~~~~~~~~^^^^^^
KeyError: 'rams_1_ram_bank_adr_i'