Ok I will now try to push this branch onto master as the initial development work here is finished:
The DE0_NANO_SOC_GHRD Quartus project produces the 2 crucial files:
socfpga.dtb (flattend device tree)
socfpga.rbf (fpga config file in raw binary format[as opposed to .sof])
!! These 2 binary files are to be loaded at boot time by spl(preloader) / u-boot, before (pre)kernel boot.
As far as the software handoff part of this project goes there is provided a customised uio driver module based upon the generic_irq.c kernel template.
This driver can autoload and is linked directly to the:
/proc/device-tree/sopc@0/bridge@0xc0000000/hm2-socfpga@0x100040000
port memory mapping hostmot2.vhd in the fpga.
The 2 files can be added online once external verification is provided
the-snowwhite
commented
8 years ago
Ok I will now try to push this branch onto master as the initial development work here is finished:
The DE0_NANO_SOC_GHRD Quartus project produces the 2 crucial files:
!! These 2 binary files are to be loaded at boot time by spl(preloader) / u-boot, before (pre)kernel boot.
As far as the software handoff part of this project goes there is provided a customised uio driver module based upon the generic_irq.c kernel template.
This driver can autoload and is linked directly to the: /proc/device-tree/sopc@0/bridge@0xc0000000/hm2-socfpga@0x100040000 port memory mapping hostmot2.vhd in the fpga.
The 2 files can be added online once external verification is provided