Hi! I stumbled upon your awesome code while implementing my own simplest riscv rv32i core in verilog/fpga. the only thing that prevented me was the mul instruction (since rv32i does not have multiplication) when calculating the djb2 hash, so I replaced it with a left shift and add. this means an overhead of a single instruction, so hopefully shouldn't affect performance that much :) obviously this is a non-critical issue, since AFAIK almost all cores in the wild support multiplication, but I think is in line with your "from scratch" ethos! also made a little addition to README to reflect this.
Hi! I stumbled upon your awesome code while implementing my own simplest riscv rv32i core in verilog/fpga. the only thing that prevented me was the mul instruction (since rv32i does not have multiplication) when calculating the djb2 hash, so I replaced it with a left shift and add. this means an overhead of a single instruction, so hopefully shouldn't affect performance that much :) obviously this is a non-critical issue, since AFAIK almost all cores in the wild support multiplication, but I think is in line with your "from scratch" ethos! also made a little addition to README to reflect this.