Creating this issue to remind myself to check whether memory barriers are required when other BCM2711 peripherals are being accessed concurrently to the GPIO device.
The BCM2711 datasheet is also not clear on whether MMIO is cache-coherent. Manual cache maintenance may be necessary.
Creating this issue to remind myself to check whether memory barriers are required when other BCM2711 peripherals are being accessed concurrently to the GPIO device.
The BCM2711 datasheet is also not clear on whether MMIO is cache-coherent. Manual cache maintenance may be necessary.