The culprit is of course Xtensa asm syntax, which makes "s32i reg, regbase, offset" looks as having 3 arguments. But in ARM syntax that would be "s32i regs, [regbase, #offset]". And in Intel syntax, the would be at all "s32i [regbase+offset], reg". So, last 2 syntactic arguments actually represent single memory reference, which is single operand if IDA terms, of type o_displ. Doing it right is important to get beyond a simple display of instructions, like doing some analysis, transformations, etc.
pfalcon
commented
9 years ago
The culprit is of course Xtensa asm syntax, which makes "s32i reg, regbase, offset" looks as having 3 arguments. But in ARM syntax that would be "s32i regs, [regbase, #offset]". And in Intel syntax, the would be at all "s32i [regbase+offset], reg". So, last 2 syntactic arguments actually represent single memory reference, which is single operand if IDA terms, of type o_displ. Doing it right is important to get beyond a simple display of instructions, like doing some analysis, transformations, etc.
I have a patch in works.