[BUG] Cache handling for IPC4 mailbox handling is implemented against best programming practices

[rfredzim]

Is your feature request related to a problem? Please describe. Currently the individual IPC4 handlers that need to access IPC payload (data past the primary/extension part) as a first step call to dcache_invalidate_region(MAILBOX_HOSTBOX_BASE) in order to force a cache update when the mailbox memory is accessed. The cache invalidation should actually end the time slot when FW accesses the data and not start such time slot.

Describe the solution you'd like IPC protocol could use the MAILBOX_HOSTBOX_BASE defined as uncached alias address, so no cache operations are needed. There should be almost none performance impact by directly accessing SRAM as usually the data from the payload is copied/used once. There seem to be no benefit from actually using L1 cache for IPC payload.

Describe alternatives you've considered Alternatively, if still using L1 cache, in the handling of IPC when the response get written to mailbox there should be a writeback + invalidate to finish such transaction. This would allow to cache being filled with SRAM contents automatically when the mailbox is accessed by the next IPC handler.

Additional context

[lgirdwood]

@rfredzim your solution looks fine to me.