Data from other layers ends up in bottom copper layer

[jordens]

Thanks for this converter! Really useful stuff.

We have a bunch of medium complexity Altium projects (all open hardware) over at Sinara and I converted a few of them to kicad.

When e.g. taking Kasli I get the following on "B.Cu":

There are a few issues:

• A lot of the items that should end up on layers like "F.SilkS" end up as copies on "B.Cu"
• Pads don't seem to be there at all
• "F/B.Mask" is empty

When opening the PCB layout in kicad (recent master), I get:

11:17:54 AM: file '/home/rj/work/m-labs/sinara/ARTIQ_ALTIUM/Kasli/PCB_Kasli/PCB_Kasli-PCBDOC.kicad_pcb', line 1: '=' expected.
11:17:54 AM: file '/home/rj/work/m-labs/sinara/ARTIQ_ALTIUM/Kasli/PCB_Kasli/PCB_Kasli-PCBDOC.kicad_pcb', line 3: '=' expected.
...
11:17:55 AM: file '/home/rj/work/m-labs/sinara/ARTIQ_ALTIUM/Kasli/PCB_Kasli/PCB_Kasli-PCBDOC.kicad_pcb', line 107304: '=' expected.
11:17:55 AM: file '/home/rj/work/m-labs/sinara/ARTIQ_ALTIUM/Kasli/PCB_Kasli/PCB_Kasli-PCBDOC.kicad_pcb', line 111495: '=' expected.

[thesourcerer8]

The PAD parsing has been improved, so please try again. Can you tell me a specific thing that ends up B.Cu that should be on F.SilkS? Coordinates and screenshot please.

[jordens]

Thanks. This is still there. Take J24 near the top left corner of the board (at X=118,Y=-246).

https://github.com/sinara-hw/Kasli fbc674e, kicad 5.0.0-rc2, git a288d61, altium2kicad f0f417f