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thixotropist / ghidra_import_tests

Experimental framework for testing Ghidra binary import support
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Add extension support to track the RVA23U64 profile and binutils testsuite #20

Closed thixotropist closed 2 months ago

thixotropist commented 5 months ago

RISCV-64 extensions can be grouped into profiles. The binutils gas assembler provides another grouping of extensions, both standard and vendor-specific. This issue tracks those extensions to show which are in need of additional import integration tests.

Binutils extension support exists in development tip:

extension version test exists? notes
e 1.9 embedded integer
i 2.1, 2.0 - base integer
m 2.0 - base integer multiply and divide
a 2.1, 2.0 - base integer atomics
f 2.2, 2.0 - base 32 bit floating point
d 2.2, 2.0 - base 64 bit floating point
q 2.2, 2.0 no quad precision floating point
c 2.0 compressed instructions
v 1.0 yes vector instructions
h 1.0 hypervisor instructions
zicbom 1.0 no cache block management
zicbop 1.0 no cache block prefetch
zicboz 1.0 no cache block zero
zicond 1.0 no integer conditional
zicntr 2.0 no performance counters
zicsr 2.0 no control and status registers
zifencei 2.0 no instruction fence
zihintntl 1.0 no locality hints
zihintpause 2.0 no pause hint
zihpm 2.0 no hardware performance monitor
zmmul 1.0 - multiply, no divide
zabha 1.0 no byte and halfword atomics
zawrs 1.0 no wait on reservation
zfa 1.0 no floating load immediate
zfh 1.0 yes 16 bit floating point
zfhmin 1.0 no minimal 16 bit floating point
zfinx 1.0 no 32 bit floating point in integer registers
zdinx 1.0 no 64 bit floating point in integer registers
zqinx 1.0 no 128 bit floating point in integer registers
zhinx 1.0 no 16 bit floating point in integer registers
zhinxmin 1.0 no minimal 16 bit floating point in integer registers
zbb 1.0 yes basic bit manipulation
zba 1.0 yes basic bit manipulation - shifts
zbc 1.0 yes carryless-multiplication
zbs 1.0 yes single bit instructions
zbkb 1.0 yes basic cryptographic support
zbkc 1.0 yes scalar crypto
zbkx 1.0 yes crossbar permutations
zk 1.0 - shorthand for _zkn_zkr_zkt
zkn 1.0 yes NIST scalar cryptography
zknd 1.0 yes AES decryption
zkne 1.0 yes AES encryption
zknh 1.0 yes sha hashing
zkr 1.0 no entropy source
zks 1.0 ? Shangmi scalar cryptography
zksed 1.0 yes SM4 block cypher encrypt/decrypt
zksh 1.0 yes SM3 hashing
zkt 1.0 - data independent execution latency
zve32x 1.0 - VLEN>=32 bits, Integer Only Vector
zve32f 1.0 - VLEN>=32 bits, 32 Bit Float Vector
zve64x 1.0 - VLEN>=64 bits, Integer Only Vector
zve64f 1.0 - VLEN>=64 bits, 32 Bit Float Support Vector
zve64d 1.0 - VLEN>=64 bits, 64 Bit Float Support Vector
zvbb 1.0 yes vector bit manipulation
zvbc 1.0 yes vector bit manipulation
zvfh 1.0 no vector 16 bit floating point
zvfhmin 1.0 no minimal vector 16 bit floating point
zvkb 1.0 yes crypto subset of zvbb
zvkg 1.0 yes Vector GCM/GMAC
zvkn 1.0 yes set of zvkned, zvknhb, zvkb, and zvkt
zvkng 1.0 yes set of zvkn and zvkg
zvknc 1.0 yes set of zvkn and zvbc
zvkned 1.0 yes vector AES block cipher
zvknha 1.0 Vector Crypto SHA-256 Secure Hash
zvknhb 1.0 Vector Crypto SHA-256 and SHA-512 Secure Hash
zvksed 1.0 yes Vector Crypto SM4
zvksh 1.0 yes Vector Crypto SM3 (Hash)
zvks 1.0 yes zvksed and zvksh
zvksg 1.0 yes zvks and zvkg
zvksc 1.0 yes zvks and zvbc
zvkt 1.0 - Vector Data-Independent Execution Latency
zvl32b 1.0 - minimum vector length 32b
zvl64b 1.0 - minimum vector length 64b
zvl128b 1.0 - minimum vector length 128b
zvl256b 1.0 - minimum vector length 256b
zvl512b 1.0 - minimum vector length 512b
zvl1024b 1.0 - minimum vector length 1024b
zvl2048b 1.0 - minimum vector length 2048b
zvl4096b 1.0 - minimum vector length 4096b
zvl8192b 1.0 - minimum vector length 8192b
zvl16384b 1.0 - minimum vector length 16384b
zvl32768b 1.0 - minimum vector length 32768b
zvl65536b 1.0 - minimum vector length 65536b
ztso 1.0 no total store ordering
zca 1.0 yes baseline added compressed instructions
zcb 1.0 yes simple added compressed instructions
zcf 1.0 no single precision compressed instructions
zcd 1.0 no double precision compressed instructions
zcmp 1.0 no push/pop and double move
smaia 1.0
smcntrpmf 1.0
smepmp 1.0
smstateen 1.0
ssaia 1.0
sscofpmf 1.0
ssstateen 1.0
sstc 1.0
svadu 1.0
svinval 1.0
svnapot 1.0
svpbmt 1.0
xcvmac 1.0
xcvalu 1.0
xtheadba 1.0 yes THead address calculations
xtheadbb 1.0 yes THead basic bit manipulation
xtheadbs 1.0 yes THead single bit instructions
xtheadcmo 1.0 yes THead cache management
xtheadcondmov 1.0 yes THead conditional move
xtheadfmemidx 1.0 yes THead floating point indexed memory instructions
xtheadfmv 1.0 yes THead double precision floating point high bit transmission
xtheadint 1.0 yes THead ipop and ipush
xtheadmac 1.0 yes THead multiply accumulate
xtheadmemidx 1.0 yes THead memory indexed instructions
xtheadmempair 1.0 yes THead memory pair instructions
xtheadsync 1.0 yes THead sync and fence
xtheadvector 1.0 no THead vector instrinsic support
xtheadzvamo 1.0 no THead vector atomics
xventanacondops 1.0 no Ventana conditional operations
xsfvcp 1.0 yes SiFive vector coprocessor interface

Additional RVA23U64 mandatory and optional ISA extensions

extension version test exists? notes
zimop no may-be-operations
zcmop no compressed may-be-operations
zcb yes compressed 8 and 18 bit load and store
zfa floating point immediate loads
zawrs no
zacas no
zvfbfwma no

Let's tackle first:

And defer:

thixotropist commented 5 months ago

d412ffc5 added the SiFive vector coprocessor extension (xsfvcp) and the 16 bit floating point extension (zfh). We don't have an encoding reference for the SiFive extension, so there is not much to do there in Ghidra. The zfh extension instructions, and their vector counterparts, may to show up first in whisper.cpp code or possibly Marvel AI accelerators.

thixotropist commented 5 months ago

Apparently the vector support for half-precision floating point (zvh) instructions doesn't actually add new opcodes. Instead, it means that SEW=16 is an acceptable value when processing opcodes like vfmul.