Add tests for newer instructions

[thixotropist]

Add test cases to generate all RISCV-64 instructions not currently handled by Ghidra but accepted by binutils 2-41. Some of these are privileged instructions used in hypervisor contexts, so their only real value is in improving the completeness of kernel disassembly. Others may include vector or crypto instructions. Prioritize instructions that might be used in a network context rather than an AI or scientific context.

[thixotropist]

We can likely track which new instructions are a priority with the industry with git log binutils/include/opcode/riscv-opc.h, looking for lines like

Date:   Fri Jun 30 22:44:05 2023 +0200
RISC-V: Add support for the Zvksh ISA extension
Zvksh is part of the vector crypto extensions

[thixotropist]

Cose this general issue with the first batch of extension instruction signatures submitted to Ghidra. More narrowly scoped issues should follow.