Closed GoogleCodeExporter closed 2 years ago
From the attached file with issues, this does not depend on the new/old style of Verilog module headers.
What steps will reproduce the problem? 1. run `iStyle --indent=tab --style=kr --suffix=".old~" --pad=all DE0_TOP.v` 2. Examine comments in module declaration 3. Find that they are changed What is the expected output? What do you see instead? The expected output is no change in the file as it has already been formatted. However, in the module declaration, the text like `CLOCK_50, // 50 MHz` becomes `CLOCK_50, // 50 MHz`. That is, there is a space added between the comma and the comment. What version of the product are you using? On what operating system? iStyle 1.20 on MacOS 10.9.2 Please provide any additional information below.
Original issue reported on code.google.com by
thomasmu...@gmail.com
on 11 Apr 2014 at 1:49Attachments:
we have similar code style, may be you can use my fork.
Original issue reported on code.google.com by
thomasmu...@gmail.com
on 11 Apr 2014 at 1:49Attachments: