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thomasrussellmurphy / istyle-verilog-formatter

Open source implementation of a Verilog formatter
GNU General Public License v2.0
173 stars 44 forks source link

try to re-enable AS_ENDMODULE and AS_MODULE #24

Closed MikeWalrus closed 2 years ago

MikeWalrus commented 2 years ago

This pull request solves the following issues that render the formatter unusable:

  1. 14

  2. Lines after the keyword endmodule are indented improperly. eg:

    // Current result
module foo();
bar bar;
endmodule

module bar();
egg egg;
endmodule

module egg();
endmodule
    
// Expected
module foo();
bar bar;
endmodule

module bar(); egg egg; endmodule

module egg(); endmodule


In fact, `module` and `endmodule`-specific logic was present in the old code but was commented out, and I have no idea why that is the case. I'm not sure whether this pull request will introduce any new bugs, but I haven't found any yet.
thomasrussellmurphy commented 2 years ago

That's certainly skipped my notice. Seems like something we want working. Thanks!

MikeWalrus commented 2 years ago

Hopefully nobody relies on the old (broken) behaviour. :)