`module` statement always indented with 8 spaces when `ifndef` compiler directive is used

thomasrussellmurphy / istyle-verilog-formatter

Open source implementation of a Verilog formatter

GNU General Public License v2.0

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Closed brlin-tw closed 4 years ago

brlin-tw commented 7 years ago

`ifndef FOO
module demo();

endmodule
`endif

$ iStyle demo.v

`ifndef FOO
module demo();

endmodule
`endif

`ifndef FOO
       module demo();

endmodule
`endif

The "module" line is always prefixed with 8 spaces, even if --indent=tabs is used
Not reproducible if ifndef is replaced with ifdef

thomasrussellmurphy commented 6 years ago

Bug acknowledged. I'll see when I have time to dig into the current declared tokens.