Closed svanimisetti closed 4 months ago
Posted the issue a little too soon. I did not realize that response to #54 by @Seas0 already listed a JTAG configuraiton file. I just combined it with the default configuration (board/sifive-hifive1-revb.cfg) to arrive at the following custom configuration file.
# This script combines the following:
#C:\apps\openocd-v0.12.0\share\openocd\scripts\interface\ftdi\tigard.cfg
#C:\apps\openocd-v0.12.0\openocd\scripts\board\sifive-hifive1-revb.cfg
adapter driver ftdi
adapter speed 4000
transport select jtag
ftdi device_desc "Tigard V1.1"
ftdi vid_pid 0x0403 0x6010
ftdi channel 1
ftdi_layout_init 0x0038 0x003b
ftdi_layout_signal nTRST -data 0x0010
ftdi_layout_signal nSRST -data 0x0020
reset_config trst_and_srst separate srst_nogate trst_push_pull srst_push_pull
set _CHIPNAME riscv
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000913
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 0x4000 -work-area-backup 0
flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME.0
init
Running using openocd.exe -f tigard_openocd_jtag_sifive_hifive1_revb02.cfg
following with targets
via telnet listed the board!
> targets
TargetName Type Endian TapName State
-- ------------------ ---------- ------ ------------------ ------------
0* riscv.cpu.0 riscv little riscv.cpu running
Resolved using combination of default scripts and solution from #54
This issue is related to #67.
I am trying to use Tigard with OpenOCD to program/debug SiFive HiFive1 Rev B02 via JTAG interface. This board is based on the RISC-V FE310-G002 microcontroller. The board has an on-board 2x5 0.05" CORTEX header with JTAG interface. See user manual for more information.
FTDIBUS (v2.12.36.4)
toWinUSB (v6.1.7600.16385)
[USB ID:0403 6010 01
]openocd.exe -f board/sifive-hifive1-revb.cfg -f interface/ftdi/tigard.cfg
), I observed the following error.Based on the previous experience with STM32, I am assuming that standard/generic configuration files may not be sufficient for interfacing the board with Tigard using OpenOCD. I could not find any issues reported on this repo with RISC-V microcontrollers or JTAG interface - so any suggestions would be greatly appreciated!