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tilk / digitaljs

Teaching-focused digital circuit simulator
BSD 2-Clause "Simplified" License
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System Verilog port input multi-dimensional array #88

Closed VasAthanasios closed 1 year ago

VasAthanasios commented 1 year ago

Greetings, I got a .sv module that uses an input port array but it looks like it's not supported

Input e.g.: _input signed [BITS-1:0] inp_name [ARRAYSIZE-1:0] Result: ERROR: syntax error, unexpected '[', expecting ',' or '=' or ')'

This is a System Verilog input style that synthesises with no issue in other software. From the README section, it is not clear if SystemVerilog is supported, but .sv files are supported. Is this a bug or multi-dimensional arrays are not supported?

In any case, thank you very much for your great work!

VasAthanasios commented 1 year ago

I did some digging and it looks like the issue is that yosys does not support multi-dimensional arrays. If you can confirm this is the issue then please close this ticket!

tilk commented 1 year ago

That's true. DigitalJS is dependent on Yosys for actual synthesis, and Yosys is unfortunately well known for its limited support of SystemVerilog features.