The data and address scrambling (ADS) is currently implemented as functions in the application_fpga top level model. It makes the top level slightly messy. It would be better if this was moved into the relevant modules - fw_ram and ram. The change should not affect FPGA resource allocation nor functionality.
Moving the functionality to other modules means that other resources will be allocated. This will probably change the generated bitstream and our digests will not match. I suggest that we close this for now.
The data and address scrambling (ADS) is currently implemented as functions in the application_fpga top level model. It makes the top level slightly messy. It would be better if this was moved into the relevant modules - fw_ram and ram. The change should not affect FPGA resource allocation nor functionality.