Open secworks opened 1 year ago
The verilator simulation builds and starts. It can respond to signals (as touch events). It also opens a pty that should be possible to use to load apps. @mchack-work will try and do that. If that works, it seems the Verilator model works.
The next step would be to decide how to integrate into the CI-flow. For example load a simple app.
Reassign to MC.
The Verilator (version 5.014) build stops with these complaints:
%Warning-UNOPTFLAT: /home/mc/tillitis/git/tillitis-key1/hw/application_fpga/rtl/rom.v:46:16: Signal unoptimizable: Circular combinational logic: 'application_fpga.rom_inst.rom_ready'
46 | reg rom_ready;
| ^~~~~~~~~
... For warning description see https://verilator.org/warn/UNOPTFLAT?v=5.014
... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
/home/mc/tillitis/git/tillitis-key1/hw/application_fpga/rtl/rom.v:46:16: Example path: application_fpga.rom_inst.rom_ready
/home/mc/tillitis/git/tillitis-key1/hw/application_fpga/tb/application_fpga_vsim.v:345:3: Example path: ALWAYS
/home/mc/tillitis/git/tillitis-key1/hw/application_fpga/tb/application_fpga_vsim.v:92:17: Example path: application_fpga.rom_cs
/home/mc/tillitis/git/tillitis-key1/hw/application_fpga/rtl/rom.v:59:3: Example path: ALWAYS
/home/mc/tillitis/git/tillitis-key1/hw/application_fpga/rtl/rom.v:46:16: Example path: application_fpga.rom_inst.rom_ready
but building with -Wno-fatal
works. However running the resulting simulation yields disappointing results:
% tkey-runapp --port /dev/pts/5 apps/blink/app.bin
Connecting to device on serial port /dev/pts/5 ...
GetNameVersion failed: ReadFrame: Read timeout
Maybe @secworks has some input on the warnings? Can we ignore them?
Did a quick check, the warnings does not seem to be present anymore while building. I have not tried to communicate with the port it gives.
But is this something that we want to finish or should we close and deprecate this?
Having a full simulator in software seems very useful for me. I don't think it's a top priority, but it would certainly help.
I can also build without warnings now. However...
% ./verilated/Vapplication_fpga
generate touch event: "$ kill -USR1 202223"
pty: /dev/pts/9
% tkey-sign --port /dev/pts/9 -G -p key.pub
WARNING: App already loaded.
GetAppNameVersion: ReadFrame: Read timeout
Couldn't load signer: no TKey on the serial port, or it's running wrong app (and is not in firmware mode)
The Verilator top level simulation seems not to work. We should debug and then add it to the CI flow.