Incremental builds for the bitstream

[dehanj]

NOTE: This branch is started from the tkey-builder-3-branch, since the newer tools are needed. This PR should wait to be merged until tkey-builder-3 is merged. tkey-builder-3 is merged, and this branch is rebased on main.

Adding support for incremental builds of the bitstream. Significantly lowers re-build times when changing the UDS and UDI.

[dehanj]

@secworks CI linting complains on the files uds.v and udi_rom.v. Any insight?

Run make lint
verilator +1364-2001ext+ --lint-only  -Wall -Wno-DECLFILENAME --timescale 1ns/1ns -DNO_ICE40_DEFAULT_ASSIGNMENTS \
-DBRAM_FW_SIZE=1536 \
-DFIRMWARE_HEX=\"/__w/tillitis-key1/tillitis-key1/hw/application_fpga/firmware.hex\" \
-DUDS_HEX=\"/__w/tillitis-key1/tillitis-key1/hw/application_fpga/data/uds.hex\" \
-DUDI_HEX=\"/__w/tillitis-key1/tillitis-key1/hw/application_fpga/data/udi.hex\" \
--top-module application_fpga \
config.vlt /__w/tillitis-key1/tillitis-key1/hw/application_fpga/rtl/application_fpga.v /__w/tillitis-key1/tillitis-key1/hw/application_fpga/rtl/clk_reset_gen.v /__w/tillitis-key1/tillitis-key1/hw/application_fpga/rtl/ram.v /__w/tillitis-key1/tillitis-key1/hw/application_fpga/rtl/rom.v /__w/tillitis-key1/tillitis-key1/hw/application_fpga/rtl/fw_ram.v /__w/tillitis-key1/tillitis-key1/hw/application_fpga/core/picorv32/rtl/picorv32.v /__w/tillitis-key1/tillitis-key1/hw/application_fpga/core/timer/rtl/timer_core.v /__w/tillitis-key1/tillitis-key1/hw/application_fpga/core/timer/rtl/timer.v /__w/tillitis-key1/tillitis-key1/hw/application_fpga/core/uds/rtl/uds.v /__w/tillitis-key1/tillitis-key1/hw/application_fpga/core/uds/rtl/uds_rom.v /__w/tillitis-key1/tillitis-key1/hw/application_fpga/core/touch_sense/rtl/touch_sense.v /__w/tillitis-key1/tillitis-key1/hw/application_fpga/core/tk1/rtl/tk1.v /__w/tillitis-key1/tillitis-key1/hw/application_fpga/core/tk1/rtl/udi_rom.v /__w/tillitis-key1/tillitis-key1/hw/application_fpga/core/uart/rtl/uart_core.v /__w/tillitis-key1/tillitis-key1/hw/application_fpga/core/uart/rtl/uart_fifo.v /__w/tillitis-key1/tillitis-key1/hw/application_fpga/core/uart/rtl/uart.v /__w/tillitis-key1/tillitis-key1/hw/application_fpga/core/trng/rtl/rosc.v /usr/local/share/yosys/ice40/cells_sim.v \
>lint_issues.txt 2>&1 \
&& { rm -f lint_issues.txt; exit 0; } \
|| {   cat lint_issues.txt; exit 1; }
%Warning-PINMISSING: /__w/tillitis-key1/tillitis-key1/hw/application_fpga/core/tk1/rtl/udi_rom.v:25:9: Cell has missing pin: 'I1'
   25 |       ) lut_i (
      |         ^~~~~
                     ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.
%Warning-PINMISSING: /__w/tillitis-key1/tillitis-key1/hw/application_fpga/core/tk1/rtl/udi_rom.v:25:9: Cell has missing pin: 'I2'
   25 |       ) lut_i (
      |         ^~~~~
%Warning-PINMISSING: /__w/tillitis-key1/tillitis-key1/hw/application_fpga/core/tk1/rtl/udi_rom.v:25:9: Cell has missing pin: 'I3'
   25 |       ) lut_i (
      |         ^~~~~
%Warning-WIDTH: /__w/tillitis-key1/tillitis-key1/hw/application_fpga/core/uds/rtl/uds.v:61:4: Input port connection 'addr' expects 3 bits on the pin connection, but pin connection's VARREF 'address' generates 8 bits.
                                                                                            : ... In instance application_fpga.uds_inst
   61 |   .addr(address),
      |    ^~~~
%Error: Exiting due to 4 warning(s)
make: *** [Makefile:183: lint] Error 1
Error: Process completed with exit code 2.

[dehanj]

Just rebased this branch on main.

[dehanj]

The linting is OK now, but this is blocked until we have tkey-builder:3 in place, tkey-builder:2 will not build using the new method.