Optimize FPGA design for clock frequency

tillitis / tillitis-key1

Board designs, FPGA verilog, firmware for TKey, the flexible and open USB security key 🔑

https://www.tillitis.se

395 stars 24 forks source link

Optimize FPGA design for clock frequency #177

Open secworks opened 6 months ago

secworks commented 6 months ago

It is quite possible that we could raise the clock frequency of the FPGA design. In order to do so we should analyze the timing after P&R and see what can be done. And then try to modify the design to improve the clock frequency.

dehanj commented 1 month ago

A first step is done, raising the frequency to 21 MHz - without doing much optimization.