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tillitis / tillitis-key1

Board designs, FPGA verilog, firmware for TKey, the flexible and open USB security key 🔑
https://www.tillitis.se
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Add a Verilog formatter #183

Open dehanj opened 6 months ago

dehanj commented 6 months ago

Adding a tool that can format Verilog helps us keeping the code clean and tidy. This should be able to run in CI, and from Makefile locally.

Verible seems like a good choice.

They even have a Github Action that can feedback directly to a PR: https://github.com/chipsalliance/verible-formatter-action

dehanj commented 1 month ago

@jthornblad Apparently you found the same tool i found earlier.

Would be good if you add you results here so we can keep track of it - if we don't include it right away.

jthornblad commented 1 month ago

@dehanj Yes, verible-verilog-format (https://github.com/chipsalliance/verible/blob/master/verilog/tools/formatter/README.md) seems to do a really good job. I have been running "verible-verilog-format --indentation_spaces=2 --wrap_end_else_clauses=true --inplace filename" and think it looks very nice.