The UDI and UDS are implemented using named instances of SB_LUT4s in the FPGA. This is all well and good. But LUT inputs are implicitly specified (in UDI). One input for UDS is used as 'read_enable', which it isn't. And the read_enable is connected to the write_enable signal for the read once-registers. Registers which are the ones that actually determine of a read access should be allowed. Note the write_emab
Finally the udi_uds_patch program writes UDI data into all 16 bits of the LUT4s, even though only two bits can be addressed.
We therefore should:
Clean up the RTL for the UDI to handle all inputs
Clean up the RTL for the UDS to use the read once-registers for access control
Clean up the patch program to not repeat the UDI data, and generally clean up the code
The UDI and UDS are implemented using named instances of SB_LUT4s in the FPGA. This is all well and good. But LUT inputs are implicitly specified (in UDI). One input for UDS is used as 'read_enable', which it isn't. And the read_enable is connected to the write_enable signal for the read once-registers. Registers which are the ones that actually determine of a read access should be allowed. Note the write_emab
Finally the udi_uds_patch program writes UDI data into all 16 bits of the LUT4s, even though only two bits can be addressed.
We therefore should: