It seems that the result from Yosys is highly dependent on how the RTL code is written. As an example nested IF-statements seems to be really bad. We should try and optimize the FPGA implementation through rewriting the code without changing the code. This may also be a reason for improving the test benches.
It seems that the result from Yosys is highly dependent on how the RTL code is written. As an example nested IF-statements seems to be really bad. We should try and optimize the FPGA implementation through rewriting the code without changing the code. This may also be a reason for improving the test benches.