Update core local Makefiles to use Verilog-2005 for sim, linting

tillitis / tillitis-key1

Board designs, FPGA verilog, firmware for TKey, the flexible and open USB security key 🔑

https://www.tillitis.se

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Update core local Makefiles to use Verilog-2005 for sim, linting #209

Closed secworks closed 5 months ago

secworks commented 5 months ago

The core local Makefiles can perform simulation and linting. They currently are set to use Verilog 2001. We should update them to be in sync with what is used for the top level. Allowing us to catch issues in the cores without running top level jobs.