This adds a simple sim model of the SB_LUT4 instance, that allows for linting of the UDS core without blowing up.
Building of the sim target breaks due to change of how the uds_rom is implemented. This needs to be fixed, but should probably be done when the uds implementation is cleaned up. For now we simply disable the failing parts of the test environment.
We should probably instead add a sim model of uds_rom. Which then would not include the SB_ROM. So any testcases would just ensure that we cam read out data, and subsequent reads are blocked.
This adds a simple sim model of the SB_LUT4 instance, that allows for linting of the UDS core without blowing up.
Building of the sim target breaks due to change of how the uds_rom is implemented. This needs to be fixed, but should probably be done when the uds implementation is cleaned up. For now we simply disable the failing parts of the test environment.