Updating submodules.

[mithro]

• litedram changed from 45da365 to c238149

  • c238149 - phy/kusddrphy: follow more Xilinx recommandations

• litepcie changed from 8bc328f to 93233fe

  • 93233fe - frontend/dma: cleanup control bits
  • 0540a88 - frontend/dma/writer: avoid stalling pipeline when not enabled

• litex changed from v0.1-319-gb7f7c8d1 to v0.1-330-g06162b61

  • 06162b61 - README: add list of supported CPUs/Cores and add link to tutorials
  • 6854c7f5 - soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/)
  • 66229c8c - add VexRiscv support (imported/adapted from misoc)
  • f60da4a5 - add VexRiscv submodule
  • d149f386 - allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32)
  • c3652935 - build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation)
  • 121eaba7 - soc/intergration/soc_core: don't delete uart/timer0 interrupts
  • 39ffa532 - xilinx/programmer: fix programmer
  • c001b8ea - build/xilinx/vivado: add vivado ip support
  • 43f8c230 - soc_core: uncomment uart interrupt deletion
  • d7c74746 - gen/sim: fix import to use litex simulator instead of migen simulator

• migen changed from 0.6.dev-99-g881741b to 0.6.dev-116-g0aa76fa

  • 0aa76fa - build/platforms: Add Arty S7 platform.
  • 19ca7d8 - platforms/tinyfpga_b: Add default serial mapping.
  • cba5bea - sayma_amc/rtm: use DIFF_TERM=TRUE on serwb lvds inputs
  • 9bc084a - Update .gitignore.
  • d46aa13 - fhdl.verilog: do not initialize combinatorial regs.
  • 02bccef - Fix breakage introduced in 2220222.
  • d667233 - LatticeIceStormToolchain: pass --no-promote-globals to arachne-pnr.
  • 2220222 - genlib.cdc.MultiReg: allow specifying reset value for registers.
  • 5c2c144 - sayma_rtm: enable OVERTEMPPOWERDOWN and use options from artiq
  • 24d0e95 - samya_amc: enable OVERTEMPPOWERDOWN
  • a32a0f7 - kasli: enable OVERTEMPPOWERDOWN
  • 81d0be3 - DDROutputImplS7: make it SAME_EDGE and fix it
  • 4039322 - kasli: mark negative polarity of mod_present on v1.1
  • b50e224 - Add DE0-Nano-SoC (aka Atlas-SoC) platform (#96)
  • c14a1e4 - Add MyStorm BlackIce I and II platforms (#95)
  • f4180e9 - vivado: print short timing info after phys_opt_design
  • c65a2f3 - vivado: run phys_opt_design after routing

Full submodule status

dcc8b8346ee4bb541c0637f3cb38349296231616 edid-decode (remotes/origin/HEAD) a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD) c23814961d71ab6508c855db3c643b71d8990e8c litedram (remotes/origin/HEAD) 33afda74f77f7bafa3e4e19641b9043320c47e4e liteeth (remotes/origin/HEAD) 93233fe196e8b7063c2293de440976497e4f6dd9 litepcie (remotes/origin/HEAD) a559afb2c53932f29ecc4cec8aa394d1004377c1 litesata (remotes/origin/HEAD) 9d5e605df3e5f1d54609acc5a2f10764045127e9 litescope (remotes/origin/HEAD) 23d6a6840d4276f8d1a7f31bafb8d0aaaecff6d1 liteusb (remotes/origin/HEAD) 9b4169d5d1e2c400a86ea0cbdb800730d84dc40b litevideo (remotes/origin/HEAD) 06162b61cb704176fea1837b804715fc7c603f48 litex (v0.1-330-g06162b61) 0aa76fa37f07641c6a95a064e0f5cd62e470b514 migen (0.6.dev-116-g0aa76fa)