DisplayPort lanes need DC-blocking (AC coupling) capacitors

[mithro]

The DisplayPort lanes and aux channel should have ~0.1uF (100nF) DC blocking capacitors between the connector and the FPGA.

The AC coupling capacitor must be in the range of 75 nF to 200 nF. A value of 100 nF is recommended. These capacitors also need to be as physically small as possible, a package size of 0201 is recommended but a 0402 is acceptable. They should be placed at the same length from the FPGA/connector.

Ported from http://redmine.numato.in/issues/1950

[mithro]

The capacitors where added to the schematic commit 4ada452b0a6dd5e9f09a80e1f66faf846f8c2c75

[mithro]

Here are a couple of designs which have the correct DC blocking capacitors;

• Atrix-7 based device;
• Cyclone-V based device using a TI redriver;

The FPGA does have built-in AC coupling in the receiver, however the design guide recommends using external AC coupling for DisplayPort. See the following picture;

[mithro]

From @anoopnumato

Is it really necessary to cut the traces and add the dc blocking capacitors on this board? Can you test current prototype without these Capacitors?

Missing the DC blocking capacitors will degrade performance, but I'm uncertain by how much (and believe it really depends on what the system is connected too). Using the internal AC coupling might (but also might not) be enough that performance is still okay for doing initial testing.

Cutting the traces and adding the capacitors can also reduce performance because the matching and grounding is no longer correct.

[mithro]

From @anoopnumato

We have tested GTP of SPN602 with out these capacitors on its reference clock and we are able verify the speed up to 3Gbs using chipscope pro.

[numato-anoopjose]

Updated the files.

[mithro]

Looks good.