[LiteX] Finish support for RISC-V in LiteX

[mithro]

Brief explanation

LiteX currently supports the lm32 and mor1k architectures and has some preliminary support for RISC-V. It would be nice if it support the RISC-V architecture fully.

Expected results

MiSoC is able to use a CPU core which supports the RISC-V architecture as an option when building SoC components.

Detailed Explanation

RISC-V

RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

Process

Steps would be;

• Figure out the best RISC-V compatible core to use.
• Figure out the toolchain needed.
• Import into MiSoC.

Some potential options are;

• https://github.com/cliffordwolf/picorv32 - PicoRV32 - A Size-Optimized RISC-V CPU
• http://fpga.org/grvi-phalanx/ ?

  Further reading

• https://github.com/m-labs/misoc
• http://riscv.org/
• http://www.lowrisc.org/
• https://en.wikipedia.org/wiki/RISC-V

[futaris]

https://twitter.com/q3k/status/955492603235053568 https://twitter.com/RohitK_Singh/status/955596375063801856

Twitter

Serge Bazanski on Twitter

“#PicoRV32 with #LiteX now boots to BIOS (after writing interrupt glue code and fixing a few other bugs on the way). Running on my ECP5-5G with fCLK at 200MHz. 9% of slices with hardware MUL/DIV enabled. Now for DRAM support on the Versa...”

Twitter

Rohit Singh on Twitter

“LiteX (by @enjoy_digital and @M_Labs_Ltd) now has PicoRV32 (by @oe1cxw) RISC-V core support, done by @q3k! Talk about awesome open-source collaboration!”

[mithro]

@futaris - Yeap!

Need to get the toolchain into conda and it would also be good to get VexRiscv imported for when you need a full RISC-V core.

[mithro]

This is done now!