Write a driver for the LiteX timer

[mithro]

It seems or1k has an timer object built into the CPU core? litex has its own timer object.

Figure out the following;

• [X] If the inbuilt or1k timer object is available on real litex SoCs? -- It's not
• [X] If we want to write a driver for the LiteX timer object -- We do
• [X] Which one we want to use under Linux -- We want the LiteX Timer

[mithro]

The litex timer object is currently broken in QEMU - https://github.com/timvideos/qemu-litex/issues/10

[mithro]

https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/mor1kx/core.py#L29 -- p_FEATURE_TIMER="NONE",

[enjoy-digital]

It seems probably better to use the litex timer in case we want to switch to another cpu (or are do you plan to only use or1k?)

[futaris]

Yep, litex timer. I'll probably just hack the kernel for now, and make a new CONFIG option for timer source later.

Just going to paste some links here for my reference:

https://github.com/timvideos/HDMI2USB-firmware-prebuilt/blob/master/archive/master/v0.0.3-703-ga16b484/mimasv2/base/or1k/software/include/generated/csr.h#L300 https://github.com/enjoy-digital/litex/blob/ab075f3d80881bc118c438f6e2684a1525a26d2f/litex/soc/software/libbase/time.c https://github.com/timvideos/linux-litex/blob/master/arch/openrisc/kernel/time.c

[mithro]

So the summary seems to be;

• The or1k timer object is disabled on real LiteX SoCs.
• We want to use the LiteX timer so we can support non-or1k architectures in the future (risc-v / j-core / maybe lm32).
• We need to write a driver for the LiteX timer object.

[tcal-x]

Hi all, is this still an open issue, or has it been superseded by other work? Thanks, Tim

[mithro]

@mateusz-holenko Would probably know the current state...

[mateusz-holenko]

@tcal-x I don't think there is a LiteX timer driver for Linux at the moment. We worked on Zephyr version which is available in mainline: https://github.com/zephyrproject-rtos/zephyr/blob/master/drivers/timer/litex_timer.c.

LiteX/VexRiscv uses VexRiscvTimer (https://github.com/enjoy-digital/litex/blob/67cf67034ca114faae91bf802424276b093df525/litex/soc/cores/cpu/vexriscv/core.py#L62) that is handled by the VexRiscv's emulator (e.g., https://github.com/SpinalHDL/VexRiscv/blob/master/src/main/c/emulator/src/hal.c#L191).

GitHub

zephyrproject-rtos/zephyr

Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures. - zephyrproject-rtos/zephyr

GitHub

enjoy-digital/litex

Build your hardware, easily! Contribute to enjoy-digital/litex development by creating an account on GitHub.

GitHub

SpinalHDL/VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation. Contribute to SpinalHDL/VexRiscv development by creating an account on GitHub.