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Bumps third_party/VexRiscv from
2942d06
tod67fe72
.Commits
d67fe72
Merge branch 'dev'1497001
Update FpuTest with the new rs1/rs2 store mapping1ee45ee
More named signals0e89ebe
Improve FPU rs1 timingse1e1be5
exception code can now be bigger than 4 bits646911a
Fix pmp write when there is hazard due to the register file.87f100d
Merge pull request #174 from lindemer/new_pmp156a84e
Fix PMP FSM halting logic342b061
Combine all the PMP logic into one FSM2a4ca0b
PMP CSR writes occur in execute stageDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
@dependabot rebase
.If all status checks pass Dependabot will automatically merge this pull request.
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