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tinyfpga / TinyFPGA-Bootloader

An open source USB bootloader for FPGAs
Apache License 2.0
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Split USB clock domains between physical and endpoint layers #40

Closed osresearch closed 5 years ago

osresearch commented 5 years ago

This patch separates the USB physical layer, which runs at 48 MHz, from the end point code, which can run at 12 to 24 MHz. This has been tested on the TinyFPGA BX and the Tomu FOMU (ice40up5k).

It also includes the patches by @smunaut to fix combinatorial loops, which allows icetime to compute timing estimates, and updates to bootloader.v and the Makefile to use nextpnr-ice40 for place and route on the BX.

mithro commented 5 years ago

@osresearch Cool! Are there some tests which can be run to confirm everything works?

osresearch commented 5 years ago

There are quite a few tests in the tests subdirectory and I've updated the wrapper to generate the slower clock (70c1234ad052e092b2d022370a80035a36300095), but all of them seems to get stuck in on tick 0 (built with iverilog v11.0):

./tests/simple_spi_in_test/a.out
VCD info: dumpfile test.vcd opened for output.
(some time later)
^C** VVP Stop(0) **
** Flushing output streams.
** Current simulation time is 0 ticks.
osresearch commented 5 years ago

This needs to be re-tested with a more recent checkout, although I don't have my programming jig handy. I can test with the existing bootloader and write into the user application space, which will hopefully be sufficient to validate.

osresearch commented 5 years ago

Merged with master and USB device enumeration seems to work on my TinyFPGA BX board. Attempting to reprogram with the bootloader running in user mode generates a metadata error, although the rest of the tinyprog communication seems to work fine.