Simulation fixes

[kgugala]

This PR fixes #51:

• adds missing files to both filelist and fusesoc core definition
• fixes simulation hangs by adding initial register values and switching to blocking assignments in combinational logic generation.

However, I see some errors in the simulation:

fusesoc --cores-root `pwd` run --run --target win10_enumeration_test TinyFPGA-Bootloader --vcd --timescale="1ps / 1ps" --continue_on_fail
INFO: Preparing ::vlog_tb_utils:1.1                                                                                                                                                                                                           
INFO: Preparing ::TinyFPGA-Bootloader:0                                                                                
INFO: Setting up project                                                                                                                                                                                                                      

INFO: Running                                                                                                          
iverilog -stop_tb -c TinyFPGA-Bootloader_0.scr -o TinyFPGA-Bootloader_0                                                
vvp -n -M. -l icarus.log -lxt2  TinyFPGA-Bootloader_0 +vcd=1                                                           
VCD info: dumpfile testlog.vcd opened for output.                                                                      
LOCATION: ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:         25                                 
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:         32                                       
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:         37                                       
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:         57                                       
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:         91                                       
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:        108                                                                                                                                                              
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:        129                                       
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:        147                                                                                                                                                              
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:        180                                       
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:        214                                       
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:        219       
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:        221                                                                                                                                                              
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:        224                                                                                                                                                              
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:        228                                                                                                                                                              
          3033216064 ERROR (top_tb.expect_usb_data): data length. usb_tx_len != length + 24                                                                                                                                                   
    actual:   008                                                                                                                                                                                                                             
    expected: 00000018                                                                                                 
          3033216064 ERROR (top_tb.expect_usb_data): data mismatch. usb_tx_data != raw_usb_data                        
    actual:   00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000005a                                                                                       
    expected: 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000004b                                                                                       
          3033216064 ERROR (top_tb.expect_usb_data): data pid mismatch. usb_tx_data[3:0] != pid                        
    actual:   a                                                                                                        
    expected: b                                            
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:        230
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:        234
          3057047872 ERROR (top_tb.expect_usb_data): data length. usb_tx_len != length + 24
    actual:   018                                          
    expected: 00000050                                     
          3057047872 ERROR (top_tb.expect_usb_data): data mismatch. usb_tx_data != raw_usb_data
    actual:   00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
0000000000000000000000000000004b
    expected: 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
0000000000000432080001000025804b
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:        252
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:        264
    ../src/TinyFPGA-Bootloader_0/tests/win10_enumeration_test/test.v:        282

looks like some IP responses are different from expected. Not sure if this is a bug in the IP or the test. @tinyfpga can you take a look on this?

[kgugala]

It looks like the issues above are in the tests, not in IP. In USB test suite (https://github.com/antmicro/usb-test-suite-testbenches/tree/rkap/tinyfpga) the tests work fine.

I think this PR can be merged as is, and the tests can be fixed in a separate PR. @tinyfpga what do you think?

[mithro]

Have you tested on real hardware?

[kgugala]

Have you tested on real hardware?

@mithro yes, it works on TinyFPGA_BX