Task list for UPduino 3.0

[vr2045]

• [x] Switch to KiCAD

Board layout:

• [x] 4 layer board, solid ground plane, dedicated power layer for 3.3V and 1.2V distribution
• [x] Any optional bridges must be done using special bridge-type footprint instead of resistors to make modification easy All passives to be no smaller than 0603 footprint
• [x] Fix silkscreen so its easy to read, add Pb Free, WEEE symbol, "Made in USA"
• [x] Move Micro USB connector inboard a little bit to allow clean depanelization

  Power

• [x] Dedicated power and ground planes
• [x] Minimum of 10uF bulk capacitance on all power rails: USB, 3.3V, 1.2V
• [x] Dedicated decoupling capacitance on each FPGA pin placed close the FPGA pin
• [x] Power decoupling per FTDI recommendations (using ferrite beads)
• [x] Change LDO's to be smaller parts, capable of 200mA max output

  Oscillator:

• [x] 12MHz crystal oscillator to replace the resonator for stability
• [x] Solder bridge option to connect the 12MHz oscillator to the FPGA

  Flash

• [x] qSPI option using the currently unused pin 10, 20 (layout permitting)
• [x] DTR capable flash to support even higher throughput

  Programming:

• [x] Connect DONE signal to the FTDI
• [x] FPGA CRAM programming capability

  LED:

• [x] Smaller 3 color LED?
• [x] Bring out the 3 color LED pins to alternate (DNI) LED footprints to allow these to be used for other applications such as IR LED's etc.

  Sample code:

• [ ] Ship with RISCV port instead of very simple blinky

  Optional

• [x] Support for the tinyFPGA bootloader by DNI'ing the FTDI for a low-cost option

[vr2045]

All the above feedback has been incorporated except for the silkscreen changes & the RISCV port.

[classic-gentleman]

All the above feedback has been incorporated except for the silkscreen changes & the RISCV port.

Really exciting development! I'm wondering though if the remaining two are to be addressed eventually; I understand you're probably testing the modifications with the customer that reported the PLL going out of phase first and foremost, but are the RISC-V and silkscreen changes planned for the 'release' version?

[classic-gentleman]

Also: when should we expect to see some bitstreams?

And: Not sure if I followed correctly (didn't look up the gerbers but only the PDF printout) but are both the FTDI and the iCE40 connected to the flash with QSPI? I can't find FLASH_M[O/I]S[I/O] routing to the FPGA, only to the FTDI. Conversely, not seeing IOB_18A/IOB_25B_G3 routing to FTDI, only to the FPGA. I am however noticing a bus switch, but it seems to just route whether CRAM or Flash is the target.

Please: What am I missing?

[vr2045]

Thank you @classic-gentleman!!! I think you found a rather major bug in the schematic in the MISO/MOSI lines. Would have cost me not only $$$ but debug/re-build time etc. Will fix this and also the silkscreen while I'm at it... I have updated the PDF schematic in GitHub with the modification. I'd like to send you a couple of the built boards as a bug bounty. If you dont mind, please send me your mailing address to sales at tinyvision dot ai.

Appreciate more sets of eyes on this! Power of open source!

• Yes, the silkscreen will get updated. Only minor changes expected. I should be able to sneak these in before I send the boards out for fab.

• RISCV port should already be there. There seem to be many floating around that are ported to the UPduino already. Since I'm maintaining the pinout for older UPduino, this should allow those ports to work with no modifications. Will add one to the Git repo when that happens.

• Bitstreams are already there :) All bitstreams meant for the UPduino from the many projects which have come up around the previous generation of this board should work with no modifications. If you see a reason why they wouldnt work, do let me know! The new additions should enable some interesting projects: external LED, qSPI for better performance, programmable IO voltage and CRAM programming.

• AFAIK, the FTDI does not support qSPI so the 2 extra flash lines for qSPI arent routed to the FTDI as you noticed.1

[classic-gentleman]

This is very kind of you!

I'm contacting you through c(...)@a(...)a.com, just so you know it's me.

When I mentioned "bitstreams" I refer to some demonstrations and exploration of the new features such as qSPI and extra PWM, indeed. I find it enticing to have a collection of "hello-word-ish" streams, especially for those wetting their feet in Verilog. Going from simple blinkenlights to a full-blown CPU core is beyond encouraging!

(I'm really fond of the LED matrix in this project: https://dadamachines.com/product/doppler/; in fact I'd love to explore switching the FTDI for an inexpensive STM32F103 "Bluepill", linking their GPIOs while still routing them to the protoboarding pins. Could give us the best of all worlds if done right; but that probably requires a fifth layer not to mess up everything, though.)

As far as eyes go, count on my pair. When the new project files are published I'll make sure to study them thoroughly.

[vr2045]

Fixed silkscreen with missing symbols and also the bug identified by @classic-gentleman . Thank you! Files updated and gerbers on Git now.

[vr2045]

Yes, I totally agree: the blinking LED gets old pretty fast. qSPI will be exercised by the processor. The external PWM pins could be used to drive a servo perhaps so its not just an old LED? Will have to think about this some more. At some point, I want to switch to Migen and the LiteX project, too many late night projects :)

I dont like the FTDI: its expensive and has only a single function. I'd rather replace it with an STM part like you suggest for not just programming but to build a more complete system with the processor+FPGA working together. This topic has been brought up in this request...

[RossBencina]

I'm just reviewing the schematic (UPduino.pdf). If I understand correctly, you've changed the behavior of the IO Bank power jumpers. As with Upduino 2.0, there are separate jumpers for VCCIO_0 and VCCIO_2. But unlike the 2.0, the options are either (1) onboard 3.3V or (2) a user supplied voltage supplied on a new edge terminal VIO_BANK_0_2.

This change suits me just fine, since I'm providing an off-board 1.8V reference, but it does appear to create a regression for 2.0 users who want to take 1.2V from the onboard regulator, since the schematic shows no user source for 1.2V. It would be nice to at least provide a solder pad exposing 1.2V for greenwire mods.

[vr2045]

Thanks for reviewing! Are you trying to make sure that the 1.2V IO voltage is supported? I changed the IO voltage for the pads intentionally away from 1.2V and this could cause an issue for users. However, as pointed out by a user on the UPduino Discord channel, the IO pads of the iCE40 are not specified for operation at 1.2V so the UPduino 2.0 with the 1.2V jumper on the IO was not correct. Also, 1.2V isnt a common IO voltage yet for most devices so not very useful even if it were within spec.

If you want the user to have access to the onboard 1.2V, this is exposed as a test point on the bottom of the board for mfg test and can also be repurposed by the user.

I hope this addresses your questions?

[RossBencina]

Yes, that addresses my questions, thank you. I did not realise that 1.2V was not a supported IO voltage,

[ghost]

Nice to see a new version of the board actually has been made :) Other thing have been taking my time (FPGA's cost a lot of time! :) ). Put my email in on the waitlist to get one ordered regardless, I like to put in my tiny bit of support :) Wish I could say I'll be able to do something with it, but have to find the time.. XD Maybe I can at least update https://github.com/cranphin/updosoc with a better tutorial for it (and update it to the latest upstream). Hackaday has done articles on the old upduino, think they might be interested in the new version? With a good risc tutorial it might have their interest, would be nice to get more people interested :)