Usage of Cluster apllication

[ashish3003]

Hi,

I have an application where I need two red pitaya working in synchronized mode. My frequencies of operations are 12 and 24 MHz respectively. Actually, it is simply a closed loop system which needs to continuously read from ADC and generate control output on DAC. One board works in 12 MHz range while other works in 24 MHz. Individually, they are working fine, but I need them to work in synchronous mode as I wish to combine their outputs. Since I don't need to put samples in BRAM (and thus get band limited) and just work up on PL part, is it possible to use your project in the said frequencies? Moreover, when I am trying to run "make all" command, it gets stuck at creating system.bd saying no files matched and system_wrapper.v does not exist. I basically want to use the block design part of synchronization logic in my project. I want to be able to run ./make_fpga_project.sh but that file seems not available. I am however, able to run Koheron's cluster project but ADC's are not in sync as written there.

Please help.

Thank you for your works.

[jonschumacher]

Hi,

I think I do not fully understand your application. Are the two frequencies only the frequencies you are sending a sine wave on or do you supply clocks with these frequencies? Is your second RP soldered as slave? How fast does your control loop have to be? Would it be fine latency-wise to just do it at the client via network? Then you would not need to modify the FPGA image. Concerning the build error it would be good to see the actual error message. And finally: How do you determine that the signals are not in sync?

Cheers Jonas

[ashish3003]

Hi Jonas,

Thanks for your response.

I think I do not fully understand your application. Are the two frequencies only the frequencies you are sending a sine wave on or do you supply clocks with these frequencies?

Yes, I am supplying sine wave of these 2 frequencies only. I do have a clock of 12 MHz available for both, but currently I am using board's clock of 125 MHz for ADC / DAC. However, I generate internal clocks of 12 and 24 MHz respectively through DDS using 125 MHz generated from PLL fed with 12 MHz clock through IN1.

it is like: 12MHz --> IN1 --> PLL --> 125 MHz --> DDS (generating 12 and 24 respectively) --> Flip-Flop CDC (fed with on board ADC clock) --> to further chain

Is your second RP soldered as slave?

No, currently they are simple RP V1.0 starter boards. But, to have the sychronization, I am ready to move resistors to R26, R27 in one of them. Moreover, I have recently bought X-Channel system also. I have tested for DAC sync over SATA connection using Koheron's cluster project in starter boards. ADC sync remains a problem now.

How fast does your control loop have to be?

It has be as fast as it can be since I wish to further this project to pulsed RF control.

Would it be fine latency-wise to just do it at the client via network?

No, I do not want client end to take this load, most of the times, this system will work on its own. Client just needs to set gains and set-points. Please let me know, if I can use your project to synchronize ADC without bandwidth limitation since I do not involve BRAM here?

And finally: How do you determine that the signals are not in sync?

Since both signals are in closed loop control, they are individually phase locked. So, when I combine them at output I do not see a stable output, rather a jumping one. Which should not be the case unless they are not in sync.

Concerning the build error it would be good to see the actual error message.

---

set errMsg "Please set the variable to a non-empty valu..." (file "src/fpga/bd/signal_calib.tcl" line 65)

 while executing

"source src/fpga/bd/signal_calib.tcl" (file "src/fpga/build.tcl" line 30) make:*** [Makefile:67: bitfiles/daq_xc7z010clg400-1.bit] Error 1

---

My vivado version is 2019.1. So, everywhere in tcl files, I have physically changed vivado version. I am currently stuck at the above error as far as installation is concerned.

Please help.

Thank you. Ashish

[jonschumacher]

Hm, then I have to ask a heretic question: Why do you want to use multiple RPs anyway? Two inputs, one output. One RP would suffice. For the clock input I would use a DIO. If your signal is actually superimposed and could be read on one ADC channel, a partial Fourier analysis with DDS would also work. If you need to use more RPs you really need to resolder the slave. It is the only way to change the main clock which I think directly feeds the ADCs which explains your sync issues. But for nothing of this you need this project here. The example from Koheron is enough. Since I do not have a Vivado 2019.1 installation around I can not check whether the version might be the issue.

[ashish3003]

Hi Jonas, I am consuming alot of resources due to modulation / demodulation and filter algorithms. So, my design jumps out of resources in case I try to fit in one RP.

If you need to use more RPs you really need to resolder the slave. It is the only way to change the main clock which I think directly feeds the ADCs which explains your sync issues.

the resistors need to be put up in External or Direct from FPGA mode? Is it just that? Will it synchronize ADC also? I thought I would need to use your project to have ADC synchronization. Please comment if I am wrong here.

Also, I tried to boot X-Channel system slave board (that already has resistors in direct from FPGA mode) with Koheron's image, it seem to be not working. I read that in case of external clock, board won't boot unless clock is provided. But in case of koheron's I need to configure the board to read clock from SATA explicitly by a python code. Can you please comment here as well?

Since I do not have a Vivado 2019.1 installation around I can not check whether the version might be the issue.

Which version would you recommend then? I actually tried older version of RedPitayaDaqServer-0.4.2 also, but resulted in same problem.

Thanks.

[jonschumacher]

I am afraid I do not have deeper insights into the stuff from Koheron. The resistor settings are described in https://tknopp.github.io/RedPitayaDAQServer/dev/cluster.html. You do not need our project for the sync. It is mainly meant for signal acquisition with streaming to a client. If you run out of resources the Z7020 variant might be a better fit. I built a real-time control for 10 frequencies and everything was fitting on one RP so maybe optimizing the algorithm design might work better for you.