FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.
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Over- and under-flow signals on all stacks (value, update, and label) #13
Fatal errors are bad, but silent failures are much much worse. Having these spill to memory is probably both hard and expensive (in cycle time). It's likely a better choice to grossly over provision the stacks and fatally fails the edge cases.
Fatal errors are bad, but silent failures are much much worse. Having these spill to memory is probably both hard and expensive (in cycle time). It's likely a better choice to grossly over provision the stacks and fatally fails the edge cases.