FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.
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Implement an alternative to Recipe (called, say, Sequential) #28
This is a generalization of issue #14. The Recipe semantics is not ideal, in particular variable assignments do not take effect in the same cycle. This makes for Verilog semantics and not C semantics, meaning in particular that Tick is semantically significant even within a sequential piece of code. As a consequence it is not possible to sprinkle Tick around the code for performance improvements or to enable stalling. The Signals have a similar inflexible semantics.
To realize the goal of enabling variable latency interactions (such as cache misses etc) I see no
alternative to designing an alternative to Recipe and migrating all of Reduceron to it.
This is a generalization of issue #14. The Recipe semantics is not ideal, in particular variable assignments do not take effect in the same cycle. This makes for Verilog semantics and not C semantics, meaning in particular that
Tickis semantically significant even within a sequential piece of code. As a consequence it is not possible to sprinkleTickaround the code for performance improvements or to enable stalling. The Signals have a similar inflexible semantics.To realize the goal of enabling variable latency interactions (such as cache misses etc) I see no alternative to designing an alternative to Recipe and migrating all of Reduceron to it.