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tommythorn / Reduceron

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.
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Replace dead link for old Reduceron project web page #41

Closed mn416 closed 2 weeks ago

mn416 commented 4 months ago

Hi @tommythorn, York seem to have deleted the old Reduceron project webpage (and many of the links it pointed to). I managed to find a copy in my archives and have rehosted it here: https://mn416.github.io/reduceron-project/. I'd be very grateful if you could update your README with the new link.

tommythorn commented 4 months ago

Thanks.

I’m on my phone right now, but I already long ago captured all the relevant docs in this very repo. Moving the link to you is just repeating the problem of external dependencies. I should either delete the reference or point to archive.org’s immutable copy.

CatsAreFluffy commented 2 weeks ago

Any updates?