tomtor / HDL-deflate

FPGA implementation of deflate (de)compress RFC 1950/1951
GNU General Public License v3.0
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How can I change the deflate core data bus width? #4

Open jackylinpda opened 3 years ago

jackylinpda commented 3 years ago

In my current design, input data width is 256bit. In deflate.v, the input i_data & output o_byte are 8bit. How can I extend the data bus to 256bit?

tomtor commented 3 years ago

you would have to write interface logic which converts from 1 256bit word to 8 8bit byte IO operations and uses an 8 byte buffer. The deflate algorithm is byte stream oriented by design.