tomverbeure / math

SpinalHDL Hardware Math Library
BSD 2-Clause "Simplified" License
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Add command line application for VHDL/Verilog generation #8

Closed fayalalebrun closed 4 months ago

fayalalebrun commented 6 months ago

This introduces a command line app which can be used to generate RTL sources for the different components in the library. Right now it is only implemented for the multiplier, adder and converter. But it will be easy to add to the others.

The implementation uses case-app, and so introduces almost no overhead per-component. Only a help message per field is required. The arguments to each component also need to be placed into a separate case class, since this case class has to be created by case-app at a time when a SpinalHDL elaboration context is not available.

In order to be more flexible with how pipeline stages are activated, I added StageMask and StageMaskConfig to allow both API and CLI users to specify which stages to enable with either a number and a mask. It also makes it easier to specify in which order pipeline stages should be activated by default.