Closed mras0 closed 2 years ago
Yeah, it was missing "extra_cycle" check. Originally CE 68000/010 was not supposed to use larger frequencies and later "extra_cycle" was missed.
Thanks!
FYI there's a minor build issue w/ memory.cpp after you've added the latest pull requests, but I imagine that'll be fixed in due time.
Closing as it seems to be fixed with the commit 3cb2d8dac82f9830a1e34cebccb219bf4979f5c9.
I'm still puzzled about the 28MHz tests, but let's save that one for when you run out of other issues to look at ;)
When WinUAE is configured to run in cycle exact mode with a 68000 clocked at more than ~7Mhz and code is running from fast mem timing involving chipmem/custom register accesses do not match experimental results (with an ACA500+). Minimal config (28Mhz)+exe: test.zip
Test executes repeated (unrolled)
TST.B (A0)
with A0=0 which takes 3 CCKs / instruction on real HW while in WinUAE (4.9.1 + latest head) it alternates between 2 and 3 CCKs.I think the issue (or at least part of it) is that
sync_cycles
in custom.cpp does not takeextra_cycle
into account.There's some discussion / test results in this vAmiga issue. Probably only interesting thing is the more elaborate "memspeed2" test program and results.
Most of the results are boring: As expected custom/chip access has to align with CCK, but I can't explain "LSR4/LSR8" tests at @ 28Mhz as I would have expected them to always take 5/6 CCKs. (LSRn is a test of
LSR D1,D0
followed byTST.B (A0)
where D1=n and A0=0).