feat(d1): add smhc driver

[jspngh]

This PR adds support for SD card interaction on the Allwinner D1 platform. It is split in an sdmmc kernel service and a driver for the SD/MMC host controller peripheral. Currently only SD card support is implemented, but this should allow for adding MMC and SDIO support later. The interface between the kernel service and the driver aims to work on the specification/protocol level and not contain any Allwinner D1 details, which should make it suitable for other platforms as well.

This PR also improves the BusGatingResetRegister trait in platforms/allwinner-d1/d1-core/src/ccu.rs

[jspngh]

I've been testing mostly with a lichee rv SOM, but have recently also started using a mango pi mq pro. On the mango pi, I'm noticing some issues with initializing the SMHC, possibly the same as when I insert the lichee rv SOM into the dock board. I'm going to try to fix this before implementing the rest of the feedback.

[hawkw]

On the mango pi, I'm noticing some issues with initializing the SMHC, possibly the same as when I insert the lichee rv SOM into the dock board. I'm going to try to fix this before implementing the rest of the feedback.

Sounds good, thanks for testing with both boards! <3

[jspngh]

On the mango pi, I'm noticing some issues with initializing the SMHC, possibly the same as when I insert the lichee rv SOM into the dock board. I'm going to try to fix this before implementing the rest of the feedback.

Sounds good, thanks for testing with both boards! <3

I think my mango pi might already be busted :frowning_face: xfel ddr d1 gives this output:

DRAM only have internal ZQ!!
get_pmu_exist() = 4294967295
ddr_efuse_type: 0x0
[AUTO DEBUG] two rank and full DQ!
ddr_efuse_type: 0x0
[AUTO DEBUG] rank 0 row = 16 
[AUTO DEBUG] rank 0 bank = 8 
[AUTO DEBUG] rank 0 page size = 8 KB 
[AUTO DEBUG] rank 1 row = 15 
[AUTO DEBUG] rank 1 bank = 8 
[AUTO DEBUG] rank 1 page size = 2 KB 
rank1 config different from rank0
DRAM BOOT DRIVE INFO: %s
DRAM CLK = 792 MHz
DRAM Type = 3 (2:DDR2,3:DDR3)
DRAMC ZQ value: 0x7b7bfb
DRAM ODT value: 0x42.
ddr_efuse_type: 0x0
DRAM SIZE =4608 M
DRAM simple test FAIL.
fedcc098 != fedcba98 at address d0000000

[hawkw]

On the mango pi, I'm noticing some issues with initializing the SMHC, possibly the same as when I insert the lichee rv SOM into the dock board.

I'm going to try to fix this before implementing the rest of the feedback.

Sounds good, thanks for testing with both boards! <3

I think my mango pi might already be busted :frowning_face:

xfel ddr d1 gives this output:

DRAM only have internal ZQ!!

get_pmu_exist() = 4294967295

ddr_efuse_type: 0x0

[AUTO DEBUG] two rank and full DQ!

ddr_efuse_type: 0x0

[AUTO DEBUG] rank 0 row = 16 

[AUTO DEBUG] rank 0 bank = 8 

[AUTO DEBUG] rank 0 page size = 8 KB 

[AUTO DEBUG] rank 1 row = 15 

[AUTO DEBUG] rank 1 bank = 8 

[AUTO DEBUG] rank 1 page size = 2 KB 

rank1 config different from rank0

DRAM BOOT DRIVE INFO: %s

DRAM CLK = 792 MHz

DRAM Type = 3 (2:DDR2,3:DDR3)

DRAMC ZQ value: 0x7b7bfb

DRAM ODT value: 0x42.

ddr_efuse_type: 0x0

DRAM SIZE =4608 M

DRAM simple test FAIL.

fedcc098 != fedcba98 at address d0000000

welp. that seems bad...

[jspngh]

welp. that seems bad...

No luck trying to revive it.

But in the meantime I've refactored the idmac code to also use a builder and bitfields. Can you have a look @hawkw to see if it's what you expected?

[jspngh]

The PR should be ready now. I went through the comments again and they all should have been resolved/applied. I still need to update the PR description for the commit message, but I'll do that another time :slightly_smiling_face:.

Let me know if I missed something or in case of other remarks!

[hawkw]

hmm, CI failure looks kinda weird, i've never seen it do that before: https://github.com/tosc-rs/mnemos/actions/runs/7008859631/job/19066205659?pr=299#step:7:876

[hawkw]

PR #300 fixes the CI issues, so updating from main should get us a green build again.