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tow3rs / catapult-v3-smartnic-re

Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
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Dragontails Peak or Longs Peak version. #1

Open mopplayer opened 3 years ago

mopplayer commented 3 years ago

Hi,

It seems that Dragontails Peak is easier to use than Longs Peak, right? I am considering to play with Dragontails Peak or Longs Peak, can you give me some suggestions?

Thank you very much.

tow3rs commented 3 years ago

Hello, I am glad to know that there is someone else messing with these boards

The main disadvantage of the Dragontails Peak are the power and PCIe connectors, to power this board and use the PCIe ports you need to solder the power cables on the PCB or on the bottom connector (J1) and the side connector (J8), another option is to build an adapter similar to Jan's one (https://github.com/j-marjanovic/ocs-tray-mezzanine-adapter).

The Longs Peak board is easier to use because it can be powered up by plugging it into a PCIe slot. Also, if the computer supports PCIe bifurcation, both PCIe lanes of the FPGA can be used without additional work.

I have three Dragontails Peak boards and two of them seem to have some hardware issues (one of the DDR4 channels can't run and the connectivity to the Mellanox NIC also seems to be broken).

mopplayer commented 3 years ago

Hi, thank you.

I am interesting on reversing engineer of those obsoleted boards. Pano Logic can build Z80 computer is so excited and then I can teach some students. But this board is not likely to do something else (general purposes). FPGA Pinouts are occupied by PCIE and DDR4 (Longs Peak version). Might desoldering be better? I did not know.

tow3rs commented 3 years ago

None of these boards are good choices for GPIO use.

The PCIe lanes are connected to the XCVR pins of the FPGA and cannot be used as general I/O. Desoldering the DRAM chips would provide a good number of GPIOs by using the ADDR and DQ/DQS signals as GPIOs, but it would be quite difficult to wire them to an external connector.

The only realistic option would be to use the LED pins as GPIO... and that would only be 9 pins.

mopplayer commented 3 years ago

Well,

I give you a new information from my board. 10AXF40GAE is the Arria 10 device (10AX115N2F40E2LG), which can be programed properly. GIT1 But we still have a long way to go. Thanks.

mopplayer commented 2 years ago

Hi, is there any updates? Could you do DCT computation through PCIE? Thanks.

tow3rs commented 2 years ago

Hello,

I'm stuck on these tasks: -The U55 I/O pinout. -Attempting to establish communication between the FPGA and the Mellanox NIC.

seldompopup commented 2 years ago

Is there anyway to disable the Mellanox on pcie variant? That thing gets pretty hot while I don't have use for it.

tow3rs commented 1 year ago

I'm not sure if the NIC can be disabled via software, but I guess it's not possible. One way to disable the NIC is to flash it with a firmware for a different device with the Mellanox tools: "flint -allow_psid_change burn".This will render the Mellanox inoperative, make sure to make a copy of the original firmware first