Closed tgtakaoka closed 6 years ago
does this close issue #28?
Yes, I think so.
I confirmed that configuring SPI on USCI A0, A1, B0, B1 of msp430f2617 are compiled without error, though I didn't confirm an actual SPI functionarilty.
do you have access to any msp4302618 or similar development boards from TI?
that is one of the x2 family processors.
I have raw msp430f2618 chip ready on breadboard in hand. I'll check SPI functionality when I find spare time.
sound good. thanks.
the approarch to the seperation looks similar to what I did on the x5 and on the msp432 code. looks good.
Sorry for the delay, but I finally found a time to confirm. SPI functionality on USCI A0, A1, B0, B1 work fine on MSP430F2618.
Please have an another look. Thanks.
The idea behind this refactoring is splitting HplMsp430UsciA and HplMsp430UsciB interfaces into four function specific interfaces.
This is just interfaces and configurations change and contains no logical difference.