Open SikoVerilog opened 1 year ago
Hello,
You can follow the instructions in CONTRIBUTING.md: https://github.com/tpoikela/uvm-python/blob/master/CONTRIBUTING.md
Briefly,
I hope I didn't miss any steps.
Hello
I want to cite your repo in my research work can you please share cite details thanks
Hello,
I found a bug on uvm_hw_reset_sequence enum is not getting name rightly which is fixed now let me know how can i commit these changes
thanks SanaUllah