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tpoikela / uvm-python

UVM 1.2 port to Python
Apache License 2.0
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Is there a way to mix SystemVerilog UVM and UVM-Python environments? #47

Open sbhutada opened 10 months ago

tpoikela commented 10 months ago

In principle yes, if you have SV UVM capable simulator. But both UVM environments would execute in parallel without synchronization. You would need to use top-level module signals or ports for communication, since this is what cocotb will see. I suggest to convert your SV UVM to uvm-python, so you can run it also with verilator or icarus, thus saving in license costs.

sbhutada commented 10 months ago

The issue is that we use SV UVM VIP from vendors. It's hard to convert those. Is there some cosim approach being looked at? Thanks.