how should I use the force function in the UVM-Python verification environment, or is there a similar function to force in UVM-Python?

[717-yq]

Hello, when using UVM-SV, sometimes I force a signal in the DUT to maintain a specific value in the sequence, so that it is not affected by the internal logic of the DUT, and then observe the changes in other signals in the DUT. So, is there a similar usage of the 'force' feature in UVM-Python?

[tpoikela]

You can use cocotb features such as Force and Release directly on signals.

https://docs.cocotb.org/en/stable/writing_testbenches.html#forcing-and-freezing-signals

[717-yq]

You can use cocotb features such as Force and Release directly on signals.您可以直接在信号上使用强制和释放等 cocotb 功能。

https://docs.cocotb.org/en/stable/writing_testbenches.html#forcing-and-freezing-signals

Thank you