trellis fails - Githubissues

FFY00 commented 4 years ago

Hi, trellis is failing here. Do you have any idea what is wrong?

ERROR: Cell 'serial_rx$tr_io' cannot be bound to bel 'X72/Y35/PIOC' since it is already bound to cell 'user_btn_n$tr_io'

Log: https://paste.xinu.at/gbppT/

trabucayre commented 4 years ago

Hi, Yes I know the issue. A serial resource is already defined using led and button pins. Modifications on my code are done. Rest to check before pushing this update. Thanks to report this issue (and force me to hurry)

FFY00 commented 4 years ago

Thank you!

trabucayre commented 4 years ago

Done! Happy to have your feedback. Thanks again

FFY00 commented 4 years ago

Thank you :grin:.

I am now running into other issue

$ ./base.py --load --cable ft232
INFO:SoC:[1m        __   _ __      _  __  [0m
INFO:SoC:[1m       / /  (_) /____ | |/_/  [0m
INFO:SoC:[1m      / /__/ / __/ -_)>  <    [0m
INFO:SoC:[1m     /____/_/\__/\__/_/|_|  [0m
INFO:SoC:[1m  Build your hardware, easily![0m
INFO:SoC:[1m--------------------------------------------------------------------------------[0m
INFO:SoC:[1mCreating SoC... (2020-07-09 18:26:51)[0m
INFO:SoC:[1m--------------------------------------------------------------------------------[0m
INFO:SoC:FPGA device : LFE5U-25F-6BG256C.
INFO:SoC:System clock: 25.00MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:[1m32[0m-bit [1mwishbone[0m Bus, [1m4.0[0mGiB Address Space.
INFO:SoCBusHandler:Adding [36mreserved[0m Bus Regions...
INFO:SoCBusHandler:Bus Handler [32mcreated[0m.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:[1m8[0m-bit CSR Bus, [1m32[0m-bit Aligned, [1m16.0[0mKiB Address Space, [1m2048[0mB Paging (Up to [1m32[0m Locations).
INFO:SoCCSRHandler:Adding [36mreserved[0m CSRs...
INFO:SoCCSRHandler:CSR Handler [32mcreated[0m.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to [1m32[0m Locations).
INFO:SoCIRQHandler:Adding [36mreserved[0m IRQs...
INFO:SoCIRQHandler:IRQ Handler [32mcreated[0m.
INFO:SoC:[1m--------------------------------------------------------------------------------[0m
INFO:SoC:[1mInitial SoC:[0m
INFO:SoC:[1m--------------------------------------------------------------------------------[0m
INFO:SoC:[1m32[0m-bit [1mwishbone[0m Bus, [1m4.0[0mGiB Address Space.
INFO:SoC:[1m8[0m-bit CSR Bus, [1m32[0m-bit Aligned, [1m16.0[0mKiB Address Space, [1m2048[0mB Paging (Up to [1m32[0m Locations).
INFO:SoC:IRQ Handler (up to [1m32[0m Locations).
INFO:SoC:[1m--------------------------------------------------------------------------------[0m
INFO:SoCCSRHandler:[4mctrl[0m CSR [36mallocated[0m at Location [1m0[0m.
INFO:SoCBusHandler:[4mio0[0m Region [32madded[0m at Origin: [1m0x80000000[0m, Size: [1m0x80000000[0m, Mode: [1mRW[0m, Cached: [1mFalse[0m Linker: [1mFalse[0m.
INFO:SoCBusHandler:[4mcpu_bus0[0m [32madded[0m as Bus Master.
INFO:SoCBusHandler:[4mcpu_bus1[0m [32madded[0m as Bus Master.
INFO:SoCCSRHandler:[4mcpu[0m CSR [36mallocated[0m at Location [1m1[0m.
INFO:SoCBusHandler:[4mrom[0m Region [32madded[0m at Origin: [1m0x00000000[0m, Size: [1m0x00008000[0m, Mode: [1mR[0m, Cached: [1mTrue[0m Linker: [1mFalse[0m.
INFO:SoCBusHandler:[4mrom[0m [32madded[0m as Bus Slave.
INFO:SoC:RAM [1mrom[0m [32madded[0m Origin: [1m0x00000000[0m, Size: [1m0x00008000[0m, Mode: [1mR[0m, Cached: [1mTrue[0m Linker: [1mFalse[0m.
INFO:SoCBusHandler:[4msram[0m Region [32madded[0m at Origin: [1m0x01000000[0m, Size: [1m0x00002000[0m, Mode: [1mRW[0m, Cached: [1mTrue[0m Linker: [1mFalse[0m.
INFO:SoCBusHandler:[4msram[0m [32madded[0m as Bus Slave.
INFO:SoC:RAM [1msram[0m [32madded[0m Origin: [1m0x01000000[0m, Size: [1m0x00002000[0m, Mode: [1mRW[0m, Cached: [1mTrue[0m Linker: [1mFalse[0m.
INFO:SoCBusHandler:[4mmain_ram[0m Region [32madded[0m at Origin: [1m0x40000000[0m, Size: [1m0x00004000[0m, Mode: [1mRW[0m, Cached: [1mTrue[0m Linker: [1mFalse[0m.
INFO:SoCBusHandler:[4mmain_ram[0m [32madded[0m as Bus Slave.
INFO:SoC:RAM [1mmain_ram[0m [32madded[0m Origin: [1m0x40000000[0m, Size: [1m0x00004000[0m, Mode: [1mRW[0m, Cached: [1mTrue[0m Linker: [1mFalse[0m.
INFO:SoCCSRHandler:[4midentifier_mem[0m CSR [36mallocated[0m at Location [1m2[0m.
INFO:SoCCSRHandler:[4muart_phy[0m CSR [36mallocated[0m at Location [1m3[0m.
INFO:SoCCSRHandler:[4muart[0m CSR [36mallocated[0m at Location [1m4[0m.
INFO:SoCIRQHandler:[4muart[0m IRQ [36mallocated[0m at Location [1m0[0m.
INFO:SoCCSRHandler:[4mtimer0[0m CSR [36mallocated[0m at Location [1m5[0m.
INFO:SoCIRQHandler:[4mtimer0[0m IRQ [36mallocated[0m at Location [1m1[0m.
INFO:SoCBusHandler:[4mcsr[0m Region [32madded[0m at Origin: [1m0x82000000[0m, Size: [1m0x00010000[0m, Mode: [1mRW[0m, Cached: [1mFalse[0m Linker: [1mFalse[0m.
INFO:SoCBusHandler:[4mcsr[0m [32madded[0m as Bus Slave.
INFO:SoCCSRHandler:[4mbridge[0m [32madded[0m as CSR Master.
INFO:SoCCSRHandler:[4mleds[0m CSR [36mallocated[0m at Location [1m6[0m.
INFO:SoC:[1m--------------------------------------------------------------------------------[0m
INFO:SoC:[1mFinalized SoC:[0m
INFO:SoC:[1m--------------------------------------------------------------------------------[0m
INFO:SoC:[1m32[0m-bit [1mwishbone[0m Bus, [1m4.0[0mGiB Address Space.
IO Regions: (1)
[4mio0[0m                 : Origin: [1m0x80000000[0m, Size: [1m0x80000000[0m, Mode: [1mRW[0m, Cached: [1mFalse[0m Linker: [1mFalse[0m
Bus Regions: (4)
[4mrom[0m                 : Origin: [1m0x00000000[0m, Size: [1m0x00008000[0m, Mode: [1mR[0m, Cached: [1mTrue[0m Linker: [1mFalse[0m
[4msram[0m                : Origin: [1m0x01000000[0m, Size: [1m0x00002000[0m, Mode: [1mRW[0m, Cached: [1mTrue[0m Linker: [1mFalse[0m
[4mmain_ram[0m            : Origin: [1m0x40000000[0m, Size: [1m0x00004000[0m, Mode: [1mRW[0m, Cached: [1mTrue[0m Linker: [1mFalse[0m
[4mcsr[0m                 : Origin: [1m0x82000000[0m, Size: [1m0x00010000[0m, Mode: [1mRW[0m, Cached: [1mFalse[0m Linker: [1mFalse[0m
Bus Masters: (2)
- [4mcpu_bus0[0m
- [4mcpu_bus1[0m
Bus Slaves: (4)
- [4mrom[0m
- [4msram[0m
- [4mmain_ram[0m
- [4mcsr[0m
INFO:SoC:[1m8[0m-bit CSR Bus, [1m32[0m-bit Aligned, [1m16.0[0mKiB Address Space, [1m2048[0mB Paging (Up to [1m32[0m Locations).
CSR Locations: (7)
- [4mctrl[0m           : [1m0[0m
- [4mcpu[0m            : [1m1[0m
- [4midentifier_mem[0m : [1m2[0m
- [4muart_phy[0m       : [1m3[0m
- [4muart[0m           : [1m4[0m
- [4mtimer0[0m         : [1m5[0m
- [4mleds[0m           : [1m6[0m
INFO:SoC:IRQ Handler (up to [1m32[0m Locations).
IRQ Locations: (2)
- [4muart[0m   : [1m0[0m
- [4mtimer0[0m : [1m1[0m
INFO:SoC:[1m--------------------------------------------------------------------------------[0m
INFO:SoCBusHandler:Interconnect: [1mInterconnectShared[0m ([1m2[0m <-> [1m4[0m).
make: Entering directory '/home/anubis/git/litexOnColorlightLab004/build/colorlight_5a_75b/software/libcompiler_rt'
make: Nothing to be done for 'all'.
make: Leaving directory '/home/anubis/git/litexOnColorlightLab004/build/colorlight_5a_75b/software/libcompiler_rt'
make: Entering directory '/home/anubis/git/litexOnColorlightLab004/build/colorlight_5a_75b/software/libbase'
 CC       exception.o
 CC       system.o
 CC       id.o
 CC       uart.o
 CC       time.o
 CC       spiflash.o
 CC       i2c.o
 CC       memtest.o
 AR       libbase.a
 AR       libbase-nofloat.a
make: Leaving directory '/home/anubis/git/litexOnColorlightLab004/build/colorlight_5a_75b/software/libbase'
make: Entering directory '/home/anubis/git/litexOnColorlightLab004/build/colorlight_5a_75b/software/liblitedram'
 CC       sdram.o
 AR       liblitedram.a
make: Leaving directory '/home/anubis/git/litexOnColorlightLab004/build/colorlight_5a_75b/software/liblitedram'
make: Entering directory '/home/anubis/git/litexOnColorlightLab004/build/colorlight_5a_75b/software/libliteeth'
 CC       udp.o
 CC       mdio.o
 AR       libliteeth.a
make: Leaving directory '/home/anubis/git/litexOnColorlightLab004/build/colorlight_5a_75b/software/libliteeth'
make: Entering directory '/home/anubis/git/litexOnColorlightLab004/build/colorlight_5a_75b/software/liblitespi'
 CC       spiflash.o
 AR       liblitespi.a
make: Leaving directory '/home/anubis/git/litexOnColorlightLab004/build/colorlight_5a_75b/software/liblitespi'
make: Entering directory '/home/anubis/git/litexOnColorlightLab004/build/colorlight_5a_75b/software/liblitesdcard'
 CC       sdcard.o
 CC       spisdcard.o
 AR       liblitesdcard.a
make: Leaving directory '/home/anubis/git/litexOnColorlightLab004/build/colorlight_5a_75b/software/liblitesdcard'
make: Entering directory '/home/anubis/git/litexOnColorlightLab004/build/colorlight_5a_75b/software/bios'
 CC       isr.o
 CC       boot.o
 CC       cmd_bios.o
 CC       cmd_mem.o
 CC       cmd_boot.o
 CC       cmd_i2c.o
 CC       cmd_spiflash.o
 CC       cmd_litedram.o
 CC       cmd_liteeth.o
 CC       cmd_litesdcard.o
 CC       main.o
 LD       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python3 -m litex.soc.software.mkmscimg bios.bin --little
python3 -m litex.soc.software.memusage bios.elf /home/anubis/git/litexOnColorlightLab004/build/colorlight_5a_75b/software/bios/../include/generated/regions.ld riscv64-elf

ROM usage: 20.64KiB     (64.49%)
RAM usage: 1.64KiB  (20.51%)

make: Leaving directory '/home/anubis/git/litexOnColorlightLab004/build/colorlight_5a_75b/software/bios'
Error: fail to open /home/anubis/git/litexOnColorlightLab004/build/colorlight_5a_75b/gateware/colorlight_5a_75b.bit
ft232

Am I doing something wrong?

And for the firmware

$ make
 CC       main.o
 CC       firmware.elf
riscv64-elf-gcc: error: ../build//software/libbase/crt0-ctr.o: No such file or directory
make: *** [Makefile:18: firmware.elf] Error 1

I fixed it by renaming crt0-ctr.o to crt0.o.

trabucayre commented 4 years ago

For the first issue (missing .bit file) have you using ./base.py --build first?

The second I need to investigate. Theorically everything is up to date on my computer...

FFY00 commented 4 years ago

Ah, :man_facepalming:. I just did ./base.py, I thought --build was implicit.

Which component is the error coming from? I can check my versions.

trabucayre commented 4 years ago

Ok. My fault. Some residual litex version in .local. I've pushed a fix.

FFY00 commented 4 years ago

I can confirm it now works, thanks!

Although I have not quite managed to make it work yet :confused:. Perhaps you could give me an hint. lxterm gets stuck.

$ lxterm /dev/ttyUSB0 --kernel firmware.bin
[LXTERM] Starting....

I have my serial adapter connected to the two most right pins of the J1 header.

http://imgur.com/a/WeDwK61

FFY00 commented 4 years ago

After flashing, pin 1 is high, which seems correct.

trabucayre commented 4 years ago

Three (maybe) stupid questions: 1/ By default this board has some 74HC245T buffers in output direction, have you changed this. In the picture it seems not. 2/ Ftdi RX -> ECP5 TX and Ftdi TX -> ECP5 RX 3/ your jtag adapter consume a ttyUSBx, are you sure to use ttyUSBx corresponding to your serial adapter?

FFY00 commented 4 years ago

Yes, stupid indeed. I totally forgot the buffer is output only. Sorry!

trabucayre commented 4 years ago

My fault (or that of the board), I wish to use button and led so the only two pins without buffer are reserved for another usage.

Tell me if the demo is working for you.

FFY00 commented 4 years ago

No no, I was aware of this, I just forgot. It's my fault.

What I ended up doing was replacing U17, as it's more isolated and I am not that used to SMD soldering, and changing the pins to J4.13, J4.15. It did not work for some reason. J4.13 is set high, but lxterm does not work.

diff --git a/base.py b/base.py
index 20aa5e3..633cd3e 100755
--- a/base.py
+++ b/base.py
@@ -21,8 +21,8 @@ from ios import Led

 _serial = [
     ("serialJ1", 0,
-        Subsignal("tx", Pins("j1:0")), # J1.1
-        Subsignal("rx", Pins("j1:1")), # J1.2
+        Subsignal("tx", Pins("j4:12")), # J4.13
+        Subsignal("rx", Pins("j4:14")), # J4.15
         IOStandard("LVCMOS33")
     ),
 ]

colorlight-u17-replacement

trabucayre commented 4 years ago

Seems good. Have you crossed RX and TX ? Are you sure for your /dev/ttyUSB ? maybe you use /dev/ttyUSBx corresponding to JTAG cable ? According to chubby75 these pins are used for all connectors, maybe a problem at this level. Last idea: lxterm display nothing when it is loaded, try to push enter key or writing serialboot followed by ? Really strange and difficult to reproduce :(

trabucayre commented 4 years ago

Hi, I've tried again with a docker (to have a clean system), changed configuration to use same pins as you. The demo is working... I have no idea why it's not working for you...

FFY00 commented 4 years ago

Okay, I will give a try again next week. I am not home so I don't have access to the board right now.

FFY00 commented 3 years ago

Hey, I have finally come back to this and I did manage to get it working, thank you! I am not sure what was going on previously.

trabucayre commented 3 years ago

Great! Thank!

trabucayre / litexOnColorlightLab004

trellis fails #2