[SYCL][FPGA][ACAP] Backport some downstream changes.

triSYCL / sycl

SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM

Other

108 stars 19 forks source link

Closed Ralender closed 2 years ago

Ralender commented 2 years ago

Factorize some functionalities such that they can be shared across SYCL passes

keryell commented 2 years ago

@lforg37 and @Ralender need to agree on this. :-)

keryell commented 2 years ago

Ping @Ralender

Ralender commented 2 years ago

This push includes the intel merge so this diff is large.

Ralender commented 2 years ago

rebased onto sycl next