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triSYCL / sycl

SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
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Update documentation to new test infrastructure #182

Closed keryell closed 1 year ago

keryell commented 2 years ago

Describe the bug

https://github.com/triSYCL/sycl/blob/sycl/unified/next/sycl/doc/GettingStartedXilinxFPGA.md should be updated around Running the test suite

Ralender commented 2 years ago

Documentation about the changes to the test infrastructure were added as part of the XRT PR so this can be closed unless you have other requests.