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triSYCL
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sycl
SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
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Merge from unified/next with Ubuntu 22.04 and Vitis 2022.1
#189
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keryell
closed
2 years ago
keryell
commented
2 years ago
What's new:
new XRT backend plugin to use AMD FPGA without the OpenCL layer;
SYCL interoperability with XRT backend;
add a new HLS-like non-single-source compiler flow relying on the C++20 features of the SYCL device-compiler to generate Vitis IP;
enable more C++ standard library in Vitis IP mode;
new
--vitis-ip-part
option to specify the FPGA target in Vitis IP mode;
new accessor property to handle HBM bank allocation;
remove default allocation on DDR bank 0;
allow N-dimensional partitioned arrays;
fix bugs in
parallel_for
emulation for FPGA with HLS flow;
updated for latest Ubuntu 22.04 Linux version;
updated for Vitis 2022.1 and latest XRT;
improved documentation;
simplify test targets;
fix many other bugs;
lot of cleanup and refactoring;
merge from upstream.
What's new:
--vitis-ip-partoption to specify the FPGA target in Vitis IP mode;parallel_foremulation for FPGA with HLS flow;