Re rebase upstream

[keryell]

I have some issues on the tests on my laptop:

∞  -<rkeryell@rk-xsj:~/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build [c75db7f0e91a]>-                                        -<pts/1>-
-<%>- cmake --build . --parallel `nproc` --target check-sycl-vitis-opencl
[0/2] Re-checking globbed directories...
[16/17] Running the SYCL regression tests for sycl-vitis hw_emu
llvm-lit: /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/sycl/test/lit.cfg.py:103: note: Backend (SYCL_BE): PI_OPENCL
llvm-lit: /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/sycl/test/lit.cfg.py:111: note: Triple: fpga64_hls_hw_emu-xilinx-linux
llvm-lit: /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/llvm/utils/lit/lit/llvm/config.py:449: note: using clang: /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/bin/clang
llvm-lit: /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/sycl/test/lit.cfg.py:141: note: Filter: opencl
llvm-lit: /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/sycl/test/lit.cfg.py:168: note: vitis mode: only
llvm-lit: /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/sycl/test/lit.cfg.py:179: note: Features: host,shell,clang,native,vitis,system-linux,target-x86_64,x86_64-linux,linux
llvm-lit: /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/sycl/test/lit.cfg.py:182: note: has opencv4: True
FAIL: SYCL :: vitis/simple_tests/single_task_vector_add.cpp (2 of 37)
******************** TEST 'SYCL :: vitis/simple_tests/single_task_vector_add.cpp' FAILED ********************
Script:
--
: 'RUN: at line 3';   rm -rf /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/tools/sycl/test/vitis/simple_tests/Output/single_task_vector_add.cpp.tmp.dir && mkdir /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/tools/sycl/test/vitis/simple_tests/Output/single_task_vector_add.cpp.tmp.dir && cd /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/tools/sycl/test/vitis/simple_tests/Output/single_task_vector_add.cpp.tmp.dir
: 'RUN: at line 4';   /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/bin/clang --driver-mode=g++  -D_GLIBCXX_ASSERTIONS=1 -std=c++20 -fsycl -fsycl-targets=fpga64_hls_hw_emu-xilinx-linux /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/sycl/test/vitis/simple_tests/single_task_vector_add.cpp -o /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/tools/sycl/test/vitis/simple_tests/Output/single_task_vector_add.cpp.tmp.dir/exec.out
: 'RUN: at line 5';   env --unset=XCL_EMULATION_MODE env SYCL_DEVICE_FILTER=opencl flock --exclusive /tmp/xrt-rkeryell.lock unshare --pid --map-current-user --kill-child timeout 600 env  /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/tools/sycl/test/vitis/simple_tests/Output/single_task_vector_add.cpp.tmp.dir/exec.out
: 'RUN: at line 7';   /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/bin/clang --driver-mode=g++  -D_GLIBCXX_ASSERTIONS=1 -std=c++20 -fsycl -fsycl-targets=fpga64_hls_hw_emu-xilinx-linux /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/sycl/test/vitis/simple_tests/single_task_vector_add.cpp -o /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/tools/sycl/test/vitis/simple_tests/Output/single_task_vector_add.cpp.tmp.dir/exec2.out --vitis-ip-part=xc7vx330t-ffg1157-1
--
Exit Code: 1

Command Output (stdout):
--
$ ":" "RUN: at line 3"
note: command had no output on stdout or stderr
$ "rm" "-rf" "/home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/tools/sycl/test/vitis/simple_tests/Output/single_task_vector_add.cpp.tmp.dir"
note: command had no output on stdout or stderr
$ "mkdir" "/home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/tools/sycl/test/vitis/simple_tests/Output/single_task_vector_add.cpp.tmp.dir"
note: command had no output on stdout or stderr
$ "cd" "/home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/tools/sycl/test/vitis/simple_tests/Output/single_task_vector_add.cpp.tmp.dir"
note: command had no output on stdout or stderr
$ ":" "RUN: at line 4"
note: command had no output on stdout or stderr
$ "/home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/bin/clang" "--driver-mode=g++" "-D_GLIBCXX_ASSERTIONS=1" "-std=c++20" "-fsycl" "-fsycl-targets=fpga64_hls_hw_emu-xilinx-linux" "/home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/sycl/test/vitis/simple_tests/single_task_vector_add.cpp" "-o" "/home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/tools/sycl/test/vitis/simple_tests/Output/single_task_vector_add.cpp.tmp.dir/exec.out"
# command output:
Option Map File Used: '/opt/xilinx/Vitis/2022.1/data/vitis/vpp/optMap.xml'

****** v++ v2022.1 (64-bit)
  **** SW Build 3524075 on 2022-04-13-17:42:45
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
    Reports: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_comp_report/handlerEE_clES2_E3add_eCM5g51B
    Log files: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_comp_log/handlerEE_clES2_E3add_eCM5g51B
Running Dispatch Server on port: 45691
INFO: [v++ 60-1548] Creating build summary session with primary output /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/handlerEE_clES2_E3add_eCM5g51B.xo.compile_summary, at Wed Aug 10 17:45:06 2022
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Aug 10 17:45:06 2022
INFO: [v++ 60-1315] Creating rulecheck session with output '/tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_comp_report/handlerEE_clES2_E3add_eCM5g51B/v++_compile_handlerEE_clES2_E3add_eCM5g51B_guidance.html', at Wed Aug 10 17:45:08 2022
INFO: [v++ 60-895]   Target platform: /opt/xilinx/platforms/xilinx_u200_gen3x16_xdma_1_202110_1/xilinx_u200_gen3x16_xdma_1_202110_1.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/opt/xilinx/platforms/xilinx_u200_gen3x16_xdma_1_202110_1/hw/hw.xsa'
INFO: [v++ 74-78] Compiler Version string: 2022.1
INFO: [v++ 60-585] Compiling for hardware emulation target
INFO: [v++ 60-423]   Target device: xilinx_u200_gen3x16_xdma_1_202110_1
INFO: [v++ 60-242] Creating kernel: 'handlerEE_clES2_E3add_eCM5g51B'

===>The following messages were generated while  performing high-level synthesis for kernel: handlerEE_clES2_E3add_eCM5g51B Log file: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_comp_tmp/handlerEE_clES2_E3add_eCM5g51B/handlerEE_clES2_E3add_eCM5g51B/vitis_hls.log :
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'Loop 1'
INFO: [v++ 204-61] Pipelining loop 'Loop 1'.
INFO: [v++ 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 3, loop 'Loop 1'
INFO: [v++ 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [v++ 200-789] **** Estimated Fmax: 411.00 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_comp_report/handlerEE_clES2_E3add_eCM5g51B/system_estimate_handlerEE_clES2_E3add_eCM5g51B.xtxt
INFO: [v++ 60-586] Created /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/handlerEE_clES2_E3add_eCM5g51B.xo
INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. 
    vitis_analyzer /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/handlerEE_clES2_E3add_eCM5g51B.xo.compile_summary 
INFO: [v++ 60-791] Total elapsed time: 0h 0m 56s
INFO: [v++ 60-1653] Closing dispatch client.
Option Map File Used: '/opt/xilinx/Vitis/2022.1/data/vitis/vpp/optMap.xml'

****** v++ v2022.1 (64-bit)
  **** SW Build 3524075 on 2022-04-13-17:42:45
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
    Reports: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_report/link
    Log files: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_log/link
Running Dispatch Server on port: 35291
INFO: [v++ 60-1548] Creating build summary session with primary output /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035.xclbin.link_summary, at Wed Aug 10 17:50:50 2022
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Wed Aug 10 17:50:50 2022
INFO: [v++ 60-1315] Creating rulecheck session with output '/tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_report/link/v++_link_single_task_vector_add-a9a035_guidance.html', at Wed Aug 10 17:50:51 2022
INFO: [v++ 60-895]   Target platform: /opt/xilinx/platforms/xilinx_u200_gen3x16_xdma_1_202110_1/xilinx_u200_gen3x16_xdma_1_202110_1.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/opt/xilinx/platforms/xilinx_u200_gen3x16_xdma_1_202110_1/hw/hw.xsa'
INFO: [v++ 74-78] Compiler Version string: 2022.1
INFO: [v++ 60-629] Linking for hardware emulation target
INFO: [v++ 60-423]   Target device: xilinx_u200_gen3x16_xdma_1_202110_1
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [17:51:01] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/handlerEE_clES2_E3add_eCM5g51B.xo -keep --xpfm /opt/xilinx/platforms/xilinx_u200_gen3x16_xdma_1_202110_1/xilinx_u200_gen3x16_xdma_1_202110_1.xpfm --target emu --output_dir /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int --temp_dir /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/sys_link
INFO: [v++ 60-1454] Run Directory: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/run_link
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Wed Aug 10 17:51:03 2022
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/handlerEE_clES2_E3add_eCM5g51B.xo
INFO: [SYSTEM_LINK 82-53] Creating IP database /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [17:51:03] build_xd_ip_db started: /opt/xilinx/Vitis/2022.1/bin/build_xd_ip_db -ip_search 0  -sds-pf /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/sys_link/hw_emu.hpfm -clkid 0 -ip /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/sys_link/iprepo/xilinx_com_hls_handlerEE_clES2_E3add_eCM5g51B_1_0,handlerEE_clES2_E3add_eCM5g51B -o /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [17:51:13] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2335.418 ; gain = 0.000 ; free physical = 5100 ; free virtual = 48547
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [17:51:13] cfgen started: /opt/xilinx/Vitis/2022.1/bin/cfgen -dmclkid 0 -r /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs: 
INFO: [CFGEN 83-0]   kernel: handlerEE_clES2_E3add_eCM5g51B, num: 1  {handlerEE_clES2_E3add_eCM5g51B_1}
INFO: [CFGEN 83-2226] Inferring mapping for argument handlerEE_clES2_E3add_eCM5g51B_1._arg_a_b to DDR[1]
INFO: [CFGEN 83-2226] Inferring mapping for argument handlerEE_clES2_E3add_eCM5g51B_1._arg_a_a to DDR[1]
INFO: [CFGEN 83-2226] Inferring mapping for argument handlerEE_clES2_E3add_eCM5g51B_1._arg_a_c to DDR[1]
INFO: [SYSTEM_LINK 82-37] [17:51:18] cfgen finished successfully
Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2335.418 ; gain = 0.000 ; free physical = 4981 ; free virtual = 48429
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [17:51:18] cf2bd started: /opt/xilinx/Vitis/2022.1/bin/cf2bd  --linux --trace_buffer 1024 --input_file /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/sys_link/_sysl/.xsd --temp_dir /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/sys_link --output_dir /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -dn dr -dp /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/sys_link/_sysl/.xsd
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [17:51:21] cf2bd finished successfully
Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2335.418 ; gain = 0.000 ; free physical = 5002 ; free virtual = 48455
INFO: [v++ 60-1441] [17:51:21] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2211.387 ; gain = 0.000 ; free physical = 5049 ; free virtual = 48501
INFO: [v++ 60-1443] [17:51:21] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/sdsl.dat -rtd /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/cf2sw.rtd -nofilter /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/cf2sw_full.rtd -xclbin /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/xclbin_orig.xml -o /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/run_link
INFO: [v++ 60-1441] [17:51:25] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2211.387 ; gain = 0.000 ; free physical = 4997 ; free virtual = 48507
INFO: [v++ 60-1443] [17:51:25] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram
INFO: [v++ 60-1454] Run Directory: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/run_link
INFO: [v++ 60-1441] [17:51:26] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.47 . Memory (MB): peak = 2211.387 ; gain = 0.000 ; free physical = 4977 ; free virtual = 48495
INFO: [v++ 60-1443] [17:51:26] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw_emu -f xilinx_u200_gen3x16_xdma_1_202110_1 --remote_ip_cache /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/tools/sycl/test/vitis/simple_tests/Output/single_task_vector_add.cpp.tmp.dir/.ipcache -s --output_dir /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int --log_dir /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_log/link --report_dir /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_report/link --config /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/vplConfig.ini -k /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link --emulation_mode debug_waveform --no-info --iprepo /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/xo/ip_repo/xilinx_com_hls_handlerEE_clES2_E3add_eCM5g51B_1_0 --messageDb /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/run_link/vpl.pb /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/run_link

****** vpl v2022.1 (64-bit)
  **** SW Build 3524075 on 2022-04-13-17:42:45
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

INFO: [VPL 60-839] Read in kernel information from file '/tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/kernel_info.dat'.
INFO: [VPL 74-78] Compiler Version string: 2022.1
INFO: [VPL 60-423]   Target device: xilinx_u200_gen3x16_xdma_1_202110_1
INFO: [VPL 60-1032] Extracting hardware platform to /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/vivado/vpl/.local/hw_platform
[17:51:48] Run vpl: Step create_project: Started
Creating Vivado project.
[17:52:30] Run vpl: Step create_project: Completed
[17:52:30] Run vpl: Step create_bd: Started
[17:52:51] Run vpl: Step create_bd: Completed
[17:52:51] Run vpl: Step update_bd: Started
[17:52:51] Run vpl: Step update_bd: Completed
[17:52:51] Run vpl: Step generate_target: Started
[17:54:08] Run vpl: Step generate_target: RUNNING...
[17:55:17] Run vpl: Step generate_target: Completed
[17:55:17] Run vpl: Step config_hw_emu.gen_scripts: Started
[17:55:31] Run vpl: Step config_hw_emu.gen_scripts: Completed
[17:55:31] Run vpl: Step config_hw_emu.compile: Started
[17:56:30] Run vpl: Step config_hw_emu.compile: Completed
[17:56:30] Run vpl: Step config_hw_emu.elaborate: Started
[17:56:54] Run vpl: Step config_hw_emu.elaborate: Completed
[17:56:54] Run vpl: FINISHED. Run Status: config_hw_emu.elaborate Complete!
INFO: [v++ 60-1441] [17:56:55] Run run_link: Step vpl: Completed
Time (s): cpu = 00:00:18 ; elapsed = 00:05:29 . Memory (MB): peak = 2211.387 ; gain = 0.000 ; free physical = 4749 ; free virtual = 45972
INFO: [v++ 60-1443] [17:56:55] Run run_link: Step rtdgen: Started
INFO: [v++ 60-1453] Command Line: rtdgen
INFO: [v++ 60-1454] Run Directory: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/run_link
INFO: [v++ 60-991] clock name 'kernel_clk/clk' (clock ID '0') is being mapped to clock name 'DATA_CLK' in the xclbin
INFO: [v++ 60-1230] The compiler selected the following frequencies for the runtime controllable kernel clock(s) and scalable system clock(s): Kernel (DATA) clock: kernel_clk/clk = 300, Kernel (KERNEL) clock: kernel_clk/clk = 300
INFO: [v++ 60-1453] Command Line: cf2sw -a /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/address_map.xml -sdsl /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/sdsl.dat -xclbin /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/xclbin_orig.xml -rtd /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/single_task_vector_add-a9a035.rtd -o /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/single_task_vector_add-a9a035.xml
INFO: [v++ 60-1652] Cf2sw returned exit code: 0
WARNING: [v++ 60-1455] Debuggable symbols are not generated successfully, clean up /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/consolidated.cf
INFO: [v++ 60-1441] [17:57:00] Run run_link: Step rtdgen: Completed
Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2211.387 ; gain = 0.000 ; free physical = 8049 ; free virtual = 49292
INFO: [v++ 60-1443] [17:57:00] Run run_link: Step xclbinutil: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --add-section BITSTREAM:RAW:/tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/behav.xse --force --target hw_emu --key-value SYS:dfx_enable:false --add-section :JSON:/tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/single_task_vector_add-a9a035.rtd --append-section :JSON:/tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/appendSection.rtd --add-section CLOCK_FREQ_TOPOLOGY:JSON:/tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/single_task_vector_add-a9a035_xml.rtd --add-section BUILD_METADATA:JSON:/tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/single_task_vector_add-a9a035_build.rtd --add-section EMBEDDED_METADATA:RAW:/tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/single_task_vector_add-a9a035.xml --add-section SYSTEM_METADATA:RAW:/tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/systemDiagramModelSlrBaseAddress.json --key-value SYS:PlatformVBNV:xilinx_u200_gen3x16_xdma_1_202110_1 --output /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035.xclbin
INFO: [v++ 60-1454] Run Directory: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/run_link
XRT Build Version: 2.14.0 (skip-hw-emu-deallocation)
       Build Date: 2022-05-06 12:19:36
          Hash ID: 87b2dcd4c07063f7650c44973837d5004dc17a36
Creating a default 'in-memory' xclbin image.

Section: 'BITSTREAM'(0) was successfully added.
Size   : 20203419 bytes
Format : RAW
File   : '/tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/behav.xse'

Section: 'MEM_TOPOLOGY'(6) was successfully added.
Format : JSON
File   : 'mem_topology'

Section: 'IP_LAYOUT'(8) was successfully added.
Format : JSON
File   : 'ip_layout'

Section: 'CONNECTIVITY'(7) was successfully added.
Format : JSON
File   : 'connectivity'

Section: 'CLOCK_FREQ_TOPOLOGY'(11) was successfully added.
Size   : 274 bytes
Format : JSON
File   : '/tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/single_task_vector_add-a9a035_xml.rtd'

Section: 'BUILD_METADATA'(14) was successfully added.
Size   : 3875 bytes
Format : JSON
File   : '/tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/single_task_vector_add-a9a035_build.rtd'

Section: 'EMBEDDED_METADATA'(2) was successfully added.
Size   : 5683 bytes
Format : RAW
File   : '/tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/single_task_vector_add-a9a035.xml'

Section: 'SYSTEM_METADATA'(22) was successfully added.
Size   : 14949 bytes
Format : RAW
File   : '/tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/int/systemDiagramModelSlrBaseAddress.json'

Section: 'PARTITION_METADATA'(20) was successfully appended to.
Format : JSON
File   : 'partition_metadata'

Section: 'IP_LAYOUT'(8) was successfully appended to.
Format : JSON
File   : 'ip_layout'
Successfully wrote (20244805 bytes) to the output file: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035.xclbin
Leaving xclbinutil.
INFO: [v++ 60-1441] [17:57:01] Run run_link: Step xclbinutil: Completed
Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2211.387 ; gain = 0.000 ; free physical = 8024 ; free virtual = 49286
INFO: [v++ 60-1443] [17:57:01] Run run_link: Step xclbinutilinfo: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --quiet --force --info /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035.xclbin.info --input /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035.xclbin
INFO: [v++ 60-1454] Run Directory: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/run_link
INFO: [v++ 60-1441] [17:57:01] Run run_link: Step xclbinutilinfo: Completed
Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2211.387 ; gain = 0.000 ; free physical = 8012 ; free virtual = 49274
INFO: [v++ 60-1443] [17:57:01] Run run_link: Step generate_sc_driver: Started
INFO: [v++ 60-1453] Command Line: 
INFO: [v++ 60-1454] Run Directory: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp/link/run_link
INFO: [v++ 60-1441] [17:57:01] Run run_link: Step generate_sc_driver: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2211.387 ; gain = 0.000 ; free physical = 8012 ; free virtual = 49274
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_report/link/system_estimate_single_task_vector_add-a9a035.xtxt
INFO: [v++ 60-586] Created /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
    Guidance: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_report/link/v++_link_single_task_vector_add-a9a035_guidance.html
    Steps Log File: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_log/link/link.steps.log

INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. 
    vitis_analyzer /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035.xclbin.link_summary 
INFO: [v++ 60-791] Total elapsed time: 0h 6m 22s
INFO: [v++ 60-1653] Closing dispatch client.
Found v++ version 2022.1
SYCL_VXX_CMD: /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/bin/opt -S --sroa-vxx-conservative --lower-mem-intr-to-llvm-type --lower-mem-intr-unroll-count=1 --unroll-only-when-forced -lower-sycl-metadata -preparesycl -loop-unroll -lower-expect -simplifycfg -sroa -early-cse -annotation2metadata -callsite-splitting -ipsccp -called-value-propagation -globalopt -mem2reg -deadargelim -simplifycfg -inline -function-attrs -sroa -early-cse-memssa -speculative-execution -jump-threading -correlated-propagation -simplifycfg -libcalls-shrinkwrap -tailcallelim -simplifycfg -reassociate -loop-simplify -lcssa -licm -loop-rotate -licm -simple-loop-unswitch -simplifycfg -loop-simplify -lcssa -indvars -loop-deletion -loop-unroll -sroa -mldst-motion -gvn -sccp -bdce -jump-threading -correlated-propagation -adce -dse -loop-simplify -lcssa -simplifycfg -elim-avail-extern -rpo-function-attrs -globalopt -globaldce -float2int -lower-constant-intrinsics -loop-simplify -lcssa -loop-rotate -loop-simplify -loop-load-elim -simplifycfg -loop-simplify -lcssa -loop-unroll -loop-simplify -lcssa -licm -alignment-from-assumptions -strip-dead-prototypes -globaldce -constmerge -loop-simplify -lcssa -loop-sink -instsimplify -div-rem-pairs -simplifycfg -inSPIRation -o /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035-kernels-prepared.ll /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035-before-opt.bc
SYCL_VXX_CMD: /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/bin/opt --lower-delayed-sycl-metadata -lower-sycl-metadata -globaldce --sycl-prepare-after-O3 -S -preparesycl -loop-unroll --unroll-only-when-forced -kernelPropGen --sycl-kernel-propgen-output /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035-kernels_properties.json -globaldce -strip-debug /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035-kernels-prepared.ll -o /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035_linked.simple.ll
SYCL_VXX_CMD: /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/bin/opt -S -vxxIRDowngrader /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035_linked.simple.ll -o /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035_kernels-linked.opt.ll
SYCL_VXX_CMD: /opt/xilinx/Vitis_HLS/2022.1/lnx64/tools/clang-3.9-csynth/bin/llvm-as /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035_kernels-linked.opt.ll -o /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035_kernels.opt.xpirbc
SYCL_VXX_CMD: /opt/xilinx/Vitis_HLS/2022.1/lnx64/tools/clang-3.9-csynth/bin/llvm-link /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035_kernels.opt.xpirbc --only-needed /opt/xilinx/Vitis_HLS/2022.1/lnx64/lib/libspir64-39-hls.bc -o /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035_kernels-linked.xpirbc
SYCL_VXX_CMD: /opt/xilinx/Vitis/2022.1/bin/v++ --target hw_emu --advanced.param compiler.hlsDataflowStrictMode=off -O3 --platform xilinx_u200_gen3x16_xdma_1_202110_1 --temp_dir /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_comp_tmp --log_dir /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_comp_log --report_dir /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_comp_report --save-temps -c -k handlerEE_clES2_E3add_eCM5g51B -o /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/handlerEE_clES2_E3add_eCM5g51B.xo /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035_kernels-linked.xpirbc
SYCL_VXX_CMD: /opt/xilinx/Vitis/2022.1/bin/v++ --target hw_emu --advanced.param compiler.hlsDataflowStrictMode=off --platform xilinx_u200_gen3x16_xdma_1_202110_1 --temp_dir /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_tmp --log_dir /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_log --report_dir /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/vxx_link_report --save-temps -l -o /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/single_task_vector_add-a9a035.xclbin /tmp/lit-tmp-2ucnebk7/single_task_vector_add-a9a035b069lknv/handlerEE_clES2_E3add_eCM5g51B.xo

$ ":" "RUN: at line 5"
note: command had no output on stdout or stderr
$ "env" "--unset=XCL_EMULATION_MODE" "env" "SYCL_DEVICE_FILTER=opencl" "flock" "--exclusive" "/tmp/xrt-rkeryell.lock" "unshare" "--pid" "--map-current-user" "--kill-child" "timeout" "600" "env" "/home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/tools/sycl/test/vitis/simple_tests/Output/single_task_vector_add.cpp.tmp.dir/exec.out"
# command output:
Queue Device: xilinx_u200_gen3x16_xdma_1_202110_1
Queue Device Vendor: Xilinx

 messages Thread is created
INFO: [HW-EMU 01] Hardware emulation runs simulation underneath. Using a large data set will result in long simulation times. It is recommended that a small dataset is used for faster execution. The flow uses approximate models for Global memories and interconnect and hence the performance data generated is approximate.
configuring dataflow mode with ert polling
scheduler config ert(1), dataflow(1), slots(16), cudma(0), cuisr(0), cdma(0), cus(1)
INFO: [HW-EMU 06-0] Waiting for the simulator process to exit
INFO: [HW-EMU 06-1] All the simulator processes exited successfully
INFO: [HW-EMU 07-0] Please refer the path "/home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/tools/sycl/test/vitis/simple_tests/Output/single_task_vector_add.cpp.tmp.dir/.run/2/hw_em/device0/binary_0/behav_waveform/xsim/simulate.log" for more detailed simulation infos, errors and warnings.

# command stderr:
XRT build version: 2.14.0
Build hash: 87b2dcd4c07063f7650c44973837d5004dc17a36
Build date: 2022-05-06 12:19:36
Git branch: skip-hw-emu-deallocation
PID: 2
UID: 1000
[Thu Aug 11 00:57:23 2022 GMT]
HOST: 
EXE: /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/tools/sycl/test/vitis/simple_tests/Output/single_task_vector_add.cpp.tmp.dir/exec.out
[XRT] WARNING: unaligned host pointer '0x2a23300' detected, this leads to extra memcpy
[XRT] WARNING: unaligned host pointer '0x2a24a00' detected, this leads to extra memcpy

$ ":" "RUN: at line 7"
note: command had no output on stdout or stderr
$ "/home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/bin/clang" "--driver-mode=g++" "-D_GLIBCXX_ASSERTIONS=1" "-std=c++20" "-fsycl" "-fsycl-targets=fpga64_hls_hw_emu-xilinx-linux" "/home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/sycl/test/vitis/simple_tests/single_task_vector_add.cpp" "-o" "/home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/tools/sycl/test/vitis/simple_tests/Output/single_task_vector_add.cpp.tmp.dir/exec2.out" "--vitis-ip-part=xc7vx330t-ffg1157-1"
# command output:

****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source /opt/xilinx/Vitis_HLS/2022.1/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/opt/xilinx/Vitis_HLS/2022.1/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'rkeryell' on host 'rk-xsj' (Linux_x86_64 version 5.15.0-46-generic) on Wed Aug 10 17:57:41 PDT 2022
INFO: [HLS 200-10] On os Ubuntu 22.04.1 LTS
INFO: [HLS 200-10] In directory '/tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g'
Sourcing Tcl script '/tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/run_hls.tcl'
INFO: [HLS 200-1510] Running: open_project -reset proj 
INFO: [HLS 200-10] Creating and opening project '/tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/proj'.
INFO: [HLS 200-1510] Running: add_files /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/single_task_vector_add-83f9a0_kernels-linked.xpirbc 
INFO: [HLS 200-10] Adding design file '/tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/single_task_vector_add-83f9a0_kernels-linked.xpirbc' to the project
INFO: [HLS 200-1510] Running: set_top handlerEE_clES2_E3add_eCM5g51B 
INFO: [HLS 200-1510] Running: open_solution -reset sol 
INFO: [HLS 200-10] Creating and opening solution '/tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/proj/sol'.
INFO: [HLS 200-10] Cleaning up the solution database.
WARNING: [HLS 200-40] No /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/proj/sol/sol.aps file found.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2022.1;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-435] Setting 'open_solution -flow_target vivado' configuration: config_interface -m_axi_latency=0
INFO: [HLS 200-1510] Running: set_part xc7vx330t-ffg1157-1 
INFO: [HLS 200-1611] Setting target device to 'xc7vx330t-ffg1157-1'
INFO: [HLS 200-1510] Running: create_clock -period 3ns -name default 
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3ns.
INFO: [HLS 200-1510] Running: config_dataflow -strict_mode off 
INFO: [HLS 200-1510] Running: csynth_design 
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 1.458 GB.
INFO: [HLS 200-10] Analyzing design file '/tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/single_task_vector_add-83f9a0_kernels-linked.xpirbc' ... 
WARNING: [HLS 207-586] overriding the module target triple with spir64-unknown-unknown
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 0.24 seconds. CPU system time: 0.09 seconds. Elapsed time: 0.17 seconds; current allocated memory: 1.458 GB.
INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
INFO: [HLS 214-241] Aggregating scalar variable '_arg_a_c9' with compact=bit mode in 64-bits
INFO: [HLS 214-241] Aggregating scalar variable '_arg_a_c8' with compact=bit mode in 64-bits
INFO: [HLS 214-241] Aggregating scalar variable '_arg_a_c7' with compact=bit mode in 64-bits
INFO: [HLS 214-241] Aggregating scalar variable '_arg_a_a6' with compact=bit mode in 64-bits
INFO: [HLS 214-241] Aggregating scalar variable '_arg_a_a5' with compact=bit mode in 64-bits
INFO: [HLS 214-241] Aggregating scalar variable '_arg_a_a4' with compact=bit mode in 64-bits
INFO: [HLS 214-241] Aggregating scalar variable '_arg_a_b3' with compact=bit mode in 64-bits
INFO: [HLS 214-241] Aggregating scalar variable '_arg_a_b2' with compact=bit mode in 64-bits
INFO: [HLS 214-241] Aggregating scalar variable '_arg_a_b1' with compact=bit mode in 64-bits
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 4.17 seconds. CPU system time: 0.62 seconds. Elapsed time: 4.28 seconds; current allocated memory: 460.688 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 460.688 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 2.42 seconds. CPU system time: 0.05 seconds. Elapsed time: 2.49 seconds; current allocated memory: 461.414 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 461.480 MB.
INFO: [XFORM 203-510] Pipelining loop 'Loop-2' in function 'handlerEE_clES2_E3add_eCM5g51B' automatically.
INFO: [XFORM 203-510] Pipelining loop 'Loop-3' in function 'handlerEE_clES2_E3add_eCM5g51B' automatically.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.05 seconds. CPU system time: 0 seconds. Elapsed time: 0.06 seconds; current allocated memory: 482.219 MB.
INFO: [HLS 200-472] Inferring partial write operation for 'array.i' 
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 482.219 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'handlerEE_clES2_E3add_eCM5g51B' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'handlerEE_clES2_E3add_eCM5g51B_Pipeline_1' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'Loop 1'.
INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 2, loop 'Loop 1'
WARNING: [HLS 200-871] Estimated clock period (2.664ns) exceeds the target (target clock period: 3ns, clock uncertainty: 0.81ns, effective delay budget: 2.19ns).
Resolution: For help on HLS 200-871 see www.xilinx.com/cgi-bin/docs/rdoc?v=2022.1;t=hls+guidance;d=200-871.html
WARNING: [HLS 200-1016] The critical path in module 'handlerEE_clES2_E3add_eCM5g51B_Pipeline_1' consists of the following:  'alloca' operation ('indvars_iv') [3]  (0 ns)
    'load' operation ('indvars_iv_load') on local variable 'indvars_iv' [8]  (0 ns)
    'getelementptr' operation ('array_i_addr') [11]  (0 ns)
    'store' operation ('array_i_addr_write_ln0') of variable 'p_arg_a_b_load_read' on array 'array_i' [12]  (2.66 ns)

Resolution: For help on HLS 200-1016 see www.xilinx.com/cgi-bin/docs/rdoc?v=2022.1;t=hls+guidance;d=200-1016.html
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.03 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.07 seconds; current allocated memory: 483.152 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 483.152 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'handlerEE_clES2_E3add_eCM5g51B' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
WARNING: [HLS 200-871] Estimated clock period (2.664ns) exceeds the target (target clock period: 3ns, clock uncertainty: 0.81ns, effective delay budget: 2.19ns).
Resolution: For help on HLS 200-871 see www.xilinx.com/cgi-bin/docs/rdoc?v=2022.1;t=hls+guidance;d=200-871.html
WARNING: [HLS 200-1016] The critical path in module 'handlerEE_clES2_E3add_eCM5g51B' consists of the following: 'alloca' operation ('array_i') [38]  (0 ns)
    'call' operation ('_ln0') to 'handlerEE_clES2_E3add_eCM5g51B_Pipeline_1' [40]  (2.66 ns)

Resolution: For help on HLS 200-1016 see www.xilinx.com/cgi-bin/docs/rdoc?v=2022.1;t=hls+guidance;d=200-1016.html
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.05 seconds. CPU system time: 0 seconds. Elapsed time: 0.05 seconds; current allocated memory: 483.152 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 483.152 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'handlerEE_clES2_E3add_eCM5g51B_Pipeline_1' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'handlerEE_clES2_E3add_eCM5g51B_Pipeline_1' pipeline 'Loop 1' pipeline type 'loop pipeline'
INFO: [RTGEN 206-100] Finished creating RTL model for 'handlerEE_clES2_E3add_eCM5g51B_Pipeline_1'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.03 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.03 seconds; current allocated memory: 483.152 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'handlerEE_clES2_E3add_eCM5g51B' 
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-500] Setting interface mode on port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_b' to 'ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_b1' to 'ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_b2' to 'ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_b3' to 'ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_a' to 'ap_vld'.
INFO: [RTGEN 206-500] Setting interface mode on port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_a4' to 'ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_a5' to 'ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_a6' to 'ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_c' to 'ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_c7' to 'ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_c8' to 'ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_c9' to 'ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on function 'handlerEE_clES2_E3add_eCM5g51B' to 'ap_ctrl_hs'.
WARNING: [RTGEN 206-101] Port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_b1' has no fanin or fanout and is left dangling.
               Please use C simulation to confirm this function argument can be read from or written to.
WARNING: [RTGEN 206-101] Port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_b2' has no fanin or fanout and is left dangling.
               Please use C simulation to confirm this function argument can be read from or written to.
WARNING: [RTGEN 206-101] Port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_b3' has no fanin or fanout and is left dangling.
               Please use C simulation to confirm this function argument can be read from or written to.
WARNING: [RTGEN 206-101] Port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_a4' has no fanin or fanout and is left dangling.
               Please use C simulation to confirm this function argument can be read from or written to.
WARNING: [RTGEN 206-101] Port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_a5' has no fanin or fanout and is left dangling.
               Please use C simulation to confirm this function argument can be read from or written to.
WARNING: [RTGEN 206-101] Port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_a6' has no fanin or fanout and is left dangling.
               Please use C simulation to confirm this function argument can be read from or written to.
WARNING: [RTGEN 206-101] Port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_c7' has no fanin or fanout and is left dangling.
               Please use C simulation to confirm this function argument can be read from or written to.
WARNING: [RTGEN 206-101] Port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_c8' has no fanin or fanout and is left dangling.
               Please use C simulation to confirm this function argument can be read from or written to.
WARNING: [RTGEN 206-101] Port 'handlerEE_clES2_E3add_eCM5g51B/p_arg_a_c9' has no fanin or fanout and is left dangling.
               Please use C simulation to confirm this function argument can be read from or written to.
INFO: [RTGEN 206-100] Finished creating RTL model for 'handlerEE_clES2_E3add_eCM5g51B'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.07 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 483.629 MB.
INFO: [RTMG 210-278] Implementing memory 'handlerEE_clES2_E3add_eCM5g51B_array_i_RAM_AUTO_1R1W_ram (RAM)' using auto RAMs.
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 0.34 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.35 seconds; current allocated memory: 488.168 MB.
INFO: [HLS 200-111] Finished Updating report files: CPU user time: 0.42 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.45 seconds; current allocated memory: 489.324 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for handlerEE_clES2_E3add_eCM5g51B.
INFO: [VLOG 209-307] Generating Verilog RTL for handlerEE_clES2_E3add_eCM5g51B.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 187.69 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 7.92 seconds. CPU system time: 0.83 seconds. Elapsed time: 8.11 seconds; current allocated memory: -1003.496 MB.
INFO: [HLS 200-1510] Running: export_design -flow impl -format ip_catalog -output /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/handlerEE_clES2_E3add_eCM5g51B.zip 
INFO: [IMPL 213-8] Exporting RTL as a Vivado IP.

****** Vivado v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source run_ippack.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/xilinx/Vivado/2022.1/data/ip'.
INFO: [Common 17-206] Exiting Vivado at Wed Aug 10 17:58:06 2022...
INFO: [IMPL 213-8] Starting RTL evaluation using Vivado ...

****** Vivado v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source run_vivado.tcl
# source ./settings.tcl
## set top_module handlerEE_clES2_E3add_eCM5g51B
## set language verilog
## set family virtex7
## set device xc7vx330t
## set package -ffg1157
## set speed -1
## set clock ap_clk
## set fsm_ext "off"
## set add_io_buffers false ;
# source -notrace ./extraction.tcl
# set vivado_proj_name project
# set vivado_proj_dir .
# set target_device "${device}${package}${speed}"
# set target_clk_period_ns "3.000"
# set target_clk_freq_hz [expr {floor(1000 / $target_clk_period_ns) * 1000000}]
# set ip_vlnv xilinx.com:hls:handlerEE_clES2_E3add_eCM5g51B:1.0
# set ip_repo_path ../ip
# set bd_design_name bd_0
# set bd_inst_name hls_inst
# set bd_props {}
# set has_synth true
# set synth_design_args {-directive sdx_optimization_effort_high}
# set synth_dcp ""
# set synth_props {}
# set has_impl 1
# set impl_props {}
# set report_options [dict create]
# dict set report_options report_level 2
# dict set report_options report_max_paths 10
# dict set report_options stdout_hls_reports 1
# dict set report_options stdout_vivado_reports 0
# dict set report_options hls_project proj
# dict set report_options hls_solution sol
# dict set report_options has_synth $has_synth
# dict set report_options has_impl $has_impl
# dict set report_options vivado_reportbasename $top_module
# dict set report_options vivado_reportdir ./report
# dict set report_options hls_impl_dir ..
# dict set report_options hls_reportdir ../report/$language
# dict set report_options target_clk_period $target_clk_period_ns
# dict set report_options target_device $target_device
# dict set report_options language $language
# dict set report_options clock_name $clock
# dict set report_options error_if_impl_timing_fails false
# dict set report_options bindmodules {handlerEE_clES2_E3add_eCM5g51B_flow_control_loop_pipe_sequential_init handlerEE_clES2_E3add_eCM5g51B_array_i_RAM_AUTO_1R1W}
# dict set report_options max_module_depth 6
# create_project $vivado_proj_name $vivado_proj_dir -part $target_device -force
create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2900.348 ; gain = 0.023 ; free physical = 4873 ; free virtual = 46521
# set_property target_language $language [current_project]
# if { ![file exists $ip_repo_path] } {
#   error "Cannot find packaged HLS IP"
# }
# set_property ip_repo_paths [file normalize $ip_repo_path] [current_project]
# update_ip_catalog
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '/tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/proj/sol/impl/ip'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/xilinx/Vivado/2022.1/data/ip'.
# create_bd_design $bd_design_name
Wrote  : </tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/proj/sol/impl/verilog/project.srcs/sources_1/bd/bd_0/bd_0.bd> 
# set cell_inst [create_bd_cell -type ip -vlnv $ip_vlnv $bd_inst_name]
# if { [llength $bd_props] } { 
#   set_property -dict $bd_props $cell_inst 
# }
# make_bd_pins_external $cell_inst
# make_bd_intf_pins_external $cell_inst
# set bd_clk_ports [get_bd_ports -filter {TYPE==clk}]
# if { [llength $bd_clk_ports] && $target_clk_freq_hz ne "" } { 
#   set_property CONFIG.FREQ_HZ $target_clk_freq_hz $bd_clk_ports 
# }
# foreach bd_port [get_bd_intf_ports] {
#   set_property name [regsub {_0$} [get_property name $bd_port] {}] $bd_port
# }
# foreach bd_port [get_bd_ports -filter {INTF!=TRUE}] {
#   set_property name [regsub {_0$} [get_property name $bd_port] {}] $bd_port
# }
# set s_axi_addr_width_min 32
WARNING: [BD 5-233] No interface ports matched 'get_bd_intf_ports -filter {MODE == "Slave" && VLNV =~ "xilinx.com:interface:aximm_rtl:*"}'
# foreach bd_port [get_bd_intf_ports -filter {MODE == "Slave" && VLNV =~ "xilinx.com:interface:aximm_rtl:*"}] {
#   set bd_port_addr_width [get_property CONFIG.ADDR_WIDTH $bd_port]
#   if { $bd_port_addr_width < $s_axi_addr_width_min } {
#     puts "INFO: Updating $bd_port CONFIG.ADDR_WIDTH to $s_axi_addr_width_min"
#     set_property CONFIG.ADDR_WIDTH $s_axi_addr_width_min $bd_port
#   }
# }
# set_msg_config -id {[BD 41-1265]} -severity {CRITICAL WARNING} -new_severity {INFO}
# assign_bd_address
Wrote  : </tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/proj/sol/impl/verilog/project.srcs/sources_1/bd/bd_0/bd_0.bd> 
Verilog Output written to : /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/proj/sol/impl/verilog/project.gen/sources_1/bd/bd_0/synth/bd_0.v
Verilog Output written to : /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/proj/sol/impl/verilog/project.gen/sources_1/bd/bd_0/sim/bd_0.v
Verilog Output written to : /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/proj/sol/impl/verilog/project.gen/sources_1/bd/bd_0/hdl/bd_0_wrapper.v
# set toprtl [make_wrapper -files [get_files ${bd_design_name}.bd] -top]
# add_files -norecurse $toprtl
# set top_inst_name [file root [file tail $toprtl]]
# puts "Using BD top: $top_inst_name"
Using BD top: bd_0_wrapper
# set xdc_files [glob -nocomplain ./*.xdc]
# if { [llength $xdc_files] } {
#     add_files -fileset constrs_1 -norecurse $xdc_files
# }
# launch_runs synth_1 -scripts_only
INFO: [BD 41-1662] The design 'bd_0.bd' is already validated. Therefore parameter propagation will not be re-run.
Verilog Output written to : /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/proj/sol/impl/verilog/project.gen/sources_1/bd/bd_0/synth/bd_0.v
Verilog Output written to : /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/proj/sol/impl/verilog/project.gen/sources_1/bd/bd_0/sim/bd_0.v
Verilog Output written to : /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/proj/sol/impl/verilog/project.gen/sources_1/bd/bd_0/hdl/bd_0_wrapper.v
INFO: [BD 41-1029] Generation completed for the IP Integrator block hls_inst .
Exporting to file /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/proj/sol/impl/verilog/project.gen/sources_1/bd/bd_0/hw_handoff/bd_0.hwh
Generated Hardware Definition File /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/proj/sol/impl/verilog/project.gen/sources_1/bd/bd_0/synth/bd_0.hwdef
WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead.
launch_runs: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 3035.016 ; gain = 72.035 ; free physical = 3840 ; free virtual = 45456
# foreach run [get_runs -filter {IS_SYNTHESIS == 1}] {
#   reset_run [get_runs $run]
# }
# set_property XPM_LIBRARIES {XPM_MEMORY XPM_FIFO} [current_project]
# hls_vivado_reports_setup $report_options
TIMESTAMP: HLS-REPORT: initialize report directories: 2022-08-10 17:58:38 PDT
# if { $has_synth || $has_impl } {
#   # synth properties setting
#   set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-mode out_of_context} -objects [get_runs synth_1]
#   set ip_inst [get_ips -quiet ${bd_design_name}*${bd_inst_name}*]
#   if { ![llength $ip_inst] } {
#       error "Cannot find HLS IP instance: ${bd_design_name}*${bd_inst_name}*"
#   }
#   set synth_run [get_runs -filter {IS_SYNTHESIS == 1} ${ip_inst}*]
#   if { ![llength $synth_run] } {
#       error "Cannot find synth run for HLS IP: ${ip_inst}*"
#   }
# 
#   if { [llength $synth_design_args] } {
#       set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value $synth_design_args -objects $synth_run
#   }
# 
#   if { [llength $synth_props] } {
#     set_property -dict $synth_props $synth_run
#   }
# 
#   # launch run synth
#   launch_runs synth_1
#   wait_on_run synth_1
#   # synth reports
#   hls_vivado_reports_synth synth_1 $report_options
#   if { $synth_dcp ne "" } {
#     file mkdir [file dirname $synth_dcp]
#     set run_dcp [glob -nocomplain [get_property DIRECTORY $synth_run]/*.dcp]
#     if { [llength $run_dcp] != 1 } { error "Cannot find single dcp file for run $synth_run" }
#     file copy -force $run_dcp $synth_dcp
#   }
# }
WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead.
[Wed Aug 10 17:58:38 2022] Launched bd_0_hls_inst_0_synth_1...
Run output will be captured here: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/proj/sol/impl/verilog/project.runs/bd_0_hls_inst_0_synth_1/runme.log
[Wed Aug 10 17:58:38 2022] Launched synth_1...
Run output will be captured here: /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/proj/sol/impl/verilog/project.runs/synth_1/runme.log
[Wed Aug 10 17:58:38 2022] Waiting for synth_1 to finish...
[Wed Aug 10 17:58:57 2022] synth_1 finished
WARNING: [Vivado 12-8222] Failed run(s) : 'bd_0_hls_inst_0_synth_1'
wait_on_runs: Time (s): cpu = 00:00:16 ; elapsed = 00:00:19 . Memory (MB): peak = 3035.016 ; gain = 0.000 ; free physical = 2996 ; free virtual = 44819
TIMESTAMP: HLS-REPORT: synthesis open_run: 2022-08-10 17:58:57 PDT
INFO: HLS-REPORT: Opening synthesis design database: open_run synth_1
ERROR: [Common 17-69] Command failed: Run 'synth_1' has not been launched. Unable to open
INFO: [Common 17-206] Exiting Vivado at Wed Aug 10 17:58:57 2022...
ERROR: [HLS 200-478] vivado returned an error 
INFO: [HLS 200-111] Finished Command export_design CPU user time: 59.68 seconds. CPU system time: 5.85 seconds. Elapsed time: 67.28 seconds; current allocated memory: 6.801 MB.
command 'ap_source' returned error code
    while executing
"source /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/run_hls.tcl"
    ("uplevel" body line 1)
    invoked from within
"uplevel \#0 [list source $arg] "

INFO: [HLS 200-112] Total CPU user time: 71.71 seconds. Total CPU system time: 7.44 seconds. Total elapsed time: 78.18 seconds; peak allocated memory: 1.458 GB.
INFO: [Common 17-206] Exiting vitis_hls at Wed Aug 10 17:58:59 2022...
Found vitis_hls version 2022.1
SYCL_VXX_CMD: /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/bin/opt -S --sroa-vxx-conservative --lower-mem-intr-to-llvm-type --lower-mem-intr-unroll-count=1 --unroll-only-when-forced -lower-sycl-metadata -preparesycl -loop-unroll -lower-expect -simplifycfg -sroa -early-cse -annotation2metadata -callsite-splitting -ipsccp -called-value-propagation -globalopt -mem2reg -deadargelim -simplifycfg -inline -function-attrs -sroa -early-cse-memssa -speculative-execution -jump-threading -correlated-propagation -simplifycfg -libcalls-shrinkwrap -tailcallelim -simplifycfg -reassociate -loop-simplify -lcssa -licm -loop-rotate -licm -simple-loop-unswitch -simplifycfg -loop-simplify -lcssa -indvars -loop-deletion -loop-unroll -sroa -mldst-motion -gvn -sccp -bdce -jump-threading -correlated-propagation -adce -dse -loop-simplify -lcssa -simplifycfg -elim-avail-extern -rpo-function-attrs -globalopt -globaldce -float2int -lower-constant-intrinsics -loop-simplify -lcssa -loop-rotate -loop-simplify -loop-load-elim -simplifycfg -loop-simplify -lcssa -loop-unroll -loop-simplify -lcssa -licm -alignment-from-assumptions -strip-dead-prototypes -globaldce -constmerge -loop-simplify -lcssa -loop-sink -instsimplify -div-rem-pairs -simplifycfg -inSPIRation -o /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/single_task_vector_add-83f9a0-kernels-prepared.ll /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/single_task_vector_add-83f9a0-before-opt.bc
SYCL_VXX_CMD: /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/bin/opt --lower-delayed-sycl-metadata -lower-sycl-metadata -globaldce --sycl-prepare-after-O3 -S -preparesycl -loop-unroll --unroll-only-when-forced -kernelPropGen --sycl-kernel-propgen-output /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/single_task_vector_add-83f9a0-kernels_properties.json -globaldce -strip-debug /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/single_task_vector_add-83f9a0-kernels-prepared.ll -o /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/single_task_vector_add-83f9a0_linked.simple.ll
SYCL_VXX_CMD: /home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/bin/opt -S -vxxIRDowngrader /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/single_task_vector_add-83f9a0_linked.simple.ll -o /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/single_task_vector_add-83f9a0_kernels-linked.opt.ll
SYCL_VXX_CMD: /opt/xilinx/Vitis_HLS/2022.1/lnx64/tools/clang-3.9-csynth/bin/llvm-as /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/single_task_vector_add-83f9a0_kernels-linked.opt.ll -o /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/single_task_vector_add-83f9a0_kernels.opt.xpirbc
SYCL_VXX_CMD: /opt/xilinx/Vitis_HLS/2022.1/lnx64/tools/clang-3.9-csynth/bin/llvm-link /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/single_task_vector_add-83f9a0_kernels.opt.xpirbc --only-needed /opt/xilinx/Vitis_HLS/2022.1/lnx64/lib/libspir64-39-hls.bc -o /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/single_task_vector_add-83f9a0_kernels-linked.xpirbc
SYCL_VXX_CMD: /opt/xilinx/Vitis_HLS/2022.1/bin/vitis_hls -f /tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/run_hls.tcl

# command stderr:
Vitis HLS invocation failed
Traceback (most recent call last):
  File "/home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/bin/sycl_vxx.py", line 452, in drive_compilation
    shutil.copy2(final, self.outpath)
  File "/usr/lib/python3.10/shutil.py", line 434, in copy2
    copyfile(src, dst, follow_symlinks=follow_symlinks)
  File "/usr/lib/python3.10/shutil.py", line 254, in copyfile
    with open(src, 'rb') as fsrc:
FileNotFoundError: [Errno 2] No such file or directory: '/tmp/lit-tmp-2ucnebk7/single_task_vector_add-83f9a0nqoucm7g/handlerEE_clES2_E3add_eCM5g51B.zip'

During handling of the above exception, another exception occurred:

Traceback (most recent call last):
  File "/home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/bin/sycl_vxx.py", line 728, in <module>
    if (not main()):
  File "/home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/bin/sycl_vxx.py", line 722, in main
    return cd.drive_compilation()
  File "/home/rkeryell/Xilinx/Projects/LLVM/worktrees/xilinx/llvm/build/bin/sycl_vxx.py", line 455, in drive_compilation
    f"Output {self.xclbin} was not properly produced by previous commands")
AttributeError: 'IPExportCompilationDriver' object has no attribute 'xclbin'
clang-15: error: sycl-link-vxx command failed with exit code 1 (use -v to see invocation)

error: command failed with exit status: 1

--

********************
                                                 -- Testing: 37 tests, 12 workers --                                                  
 78% [========================================================================================-------------------------] ETA: 00:04:16
SYCL :: vitis/simple_tests/single_task_vector_add.cpp                                                                                 

It is not clear what the error failure is. It looks like there are several tests intermixed. I can see --vitis-ip-part=xc7vx330t-ffg1157-1 along some xilinx_u200_gen3x16_xdma_1_202110_1. Perhaps my XILINX_PLATFORM=xilinx_u200_gen3x16_xdma_1_202110_1 does some interference or the xc7vx330t-ffg1157-1 is not in the list of devices coming by default with /opt/xilinx? What are you validating against?

[keryell]

@Ralender I made some progress with this snapshot https://github.com/Ralender/sycl/pull/1

[keryell]

Thanks. I will do some polishing with another branch later.